revyos / xuantie-c900-bugsLinks
Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920
☆25Updated 4 months ago
Alternatives and similar repositories for xuantie-c900-bugs
Users that are interested in xuantie-c900-bugs are comparing it to the libraries listed below
Sorting:
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support☆41Updated 2 months ago
- Wrappers for open source FPU hardware implementations.☆35Updated last year
- A extremely size-optimized RV32I soft processor for FPGA.☆28Updated 7 years ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆20Updated 3 years ago
- The 'missing header' for Chisel☆21Updated 7 months ago
- RISC-V Online Help☆35Updated 3 months ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Updated last year
- Remote JTAG server for remote debugging☆43Updated last year
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- My knowledge base☆72Updated last week
- Examine and discover LoongArch instructions☆21Updated 4 months ago
- A riscv emulator.☆19Updated last year
- Unofficial LoongArch Intrinsics Guide☆62Updated 3 months ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- A tool to convert binary files to COE files 💫☆16Updated last month
- Microarchitecture diagrams of several CPUs☆43Updated last month
- User-mode trap-and-emulate hypervisor for RISC-V☆14Updated 3 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Updated 8 months ago
- ☆39Updated last week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last week
- RISC-V Online Assembler using Emscripten, Gnu Binutils☆58Updated 2 years ago
- Open-Source EDA workshop for RISC-V community☆12Updated 3 years ago
- ☆10Updated 5 years ago
- RISC-V Summit China 2023☆40Updated 2 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 4 years ago
- ☆34Updated 3 years ago
- Dump Apple PMU counter definitions from `/usr/share/kpep` in macOS☆16Updated last month
- Nix template for the chisel-based industrial designing flows.☆48Updated 6 months ago
- Run Rocket Chip on VCU128☆30Updated 3 weeks ago