Alternatives and similar repositories for python-to-verilog:

Users that are interested in python-to-verilog are comparing it to the libraries listed below

• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆27Updated 5 years ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 7 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 5 years ago
• JoseIuri / UVM_Python_UVMC
  This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…
  ☆16Updated 5 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆22Updated 2 months ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆17Updated 6 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆33Updated 7 years ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago
• PacoReinaCampo / SoC-DV
  System on Chip verified with UVM/OSVVM/FV
  ☆25Updated this week
• thinkoco / systemverilog-python
  Systemverilog DPI-C call Python function
  ☆22Updated 4 years ago
• alice820621 / A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM
  A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…
  ☆15Updated 6 years ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• smartfoxdata / uvm_apb
  uvm_apb is a uvm package for modeling and verifying APB (Advanced Periperal Bus) protocol
  ☆20Updated 2 months ago
• xdesigns / 4way-cache
  Verilog cache implementation of 4-way FIFO 16k Cache
  ☆19Updated 12 years ago
• Gateway91 / AHB-APB_Bridge_UVM_Env
  AHB-APB UVM Verification Environment
  ☆17Updated 9 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆11Updated 4 years ago
• pulp-platform / axi2apb
  ☆20Updated 5 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆33Updated 9 years ago
• muneebullashariff / pulpino_soc_uvm_testbench
  UVM testbench for verifying the Pulpino SoC
  ☆13Updated 5 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆31Updated 2 years ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 6 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆22Updated 6 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 11 months ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• ljgibbslf / basic_cache_core
  ☆27Updated 4 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago
• yuhsuan-t / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆19Updated 7 years ago
• vinodsake / Last-Level-Cache-Simulator
  ☆12Updated 8 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆25Updated 5 years ago