Alternatives and similar repositories for DongshanPI-D1s_BareMetal:

Users that are interested in DongshanPI-D1s_BareMetal are comparing it to the libraries listed below

• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆26Updated 3 years ago
• metro94 / RV-DAP-Plus
  ☆25Updated 3 years ago
• wuhanstudio / picorv32_tang
  A 32-bit RISC-V SoC on FPGA that supports RT-Thread.
  ☆28Updated last year
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆24Updated 3 years ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆24Updated 4 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆25Updated 4 years ago
• balmerdx / sdio_linux_fpga
  Communication channel from FPGA (Alterra EP4CE10) and Linux (Lichee PI Allwinner V3S)
  ☆29Updated 5 years ago
• wuhanstudio / picorv32_EG4S20
  A 32-bit RISC-V SoC on FPGA that supports RT-Thread.
  ☆13Updated last year
• baochuquan / RISCV-MMU
  ☆14Updated 7 years ago
• pablomarx / rodinia
  AGM bitstream utilities and decoded files from Supra
  ☆42Updated last year
• AlSaqr-platform / he-soc
  ☆31Updated 3 weeks ago
• kangyuzhe666 / zynq7010-pynq-2.5
  蚂蚁S9矿板移植pynq2.5
  ☆26Updated 4 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆37Updated 3 years ago
• libc0607 / ch552-ag1k-msd
  Load bitstream to AG1K series FPGA using CH552
  ☆12Updated 3 years ago
• hydrausb3 / wch-ch569-serdes
  WCH CH569 SerDes Reverse Engineering
  ☆26Updated 2 years ago
• nucleisys / n200-doc
  Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php
  ☆25Updated 4 years ago
• OldRepoPreservation / mpeg2fpga
  An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.
  ☆22Updated 5 years ago
• SoCXin / RISC-V
  RISC-V Architecture
  ☆20Updated 2 years ago
• Harry2005 / Thunderbolt3
  A module for TBT3
  ☆33Updated last year
• YuzukiHD / YuzukiNezha-D1s
  YuzukiNezha D1s is a SOM based on Allwinner D1s
  ☆15Updated 3 years ago
• shenyaming / riscv-fpga
  Share JTAG chain within RISCV core and Xilinx FPGA.
  ☆9Updated 5 years ago
• ymz000 / Kintex-7-xc7k325-pcb
  基于Kintex-7 XC7K325T的高性能FPGA功能验证板
  ☆19Updated 5 years ago
• CospanDesign / nysa-sdio-device
  SDIO Device Verilog Core
  ☆22Updated 6 years ago
• wuhanstudio / hbird_e203_tang
  A 32bit RISC-V SoC on FPGA (EG4S20) that supports RT-Thread.
  ☆12Updated 4 years ago
• freecores / usb_phy
  USB 1.1 PHY
  ☆10Updated 10 years ago
• freecores / turbo8051
  turbo 8051
  ☆29Updated 7 years ago
• XIVN1987 / Blaster
  Altera USB Blaster porting to Artery AT32F425 and WCH CH32V203.
  ☆20Updated last year
• FarisHijazi / LZ4-Decompressor-Verilog
  Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language
  ☆15Updated 6 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆21Updated 10 years ago
• regymm / SqueakyBoard
  My self-designed ZYNQ-7010 4-layer developement board.
  ☆31Updated 3 years ago