平头哥无剑100开源SoC平台（双核E902，安全启动，BootROM，IOPMP，Mailbox，RSA-2048，SHA-2， WS2812，Flash）
☆23Sep 2, 2023Updated 3 years ago
Alternatives and similar repositories for wujian100_open
Users that are interested in wujian100_open are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆14Sep 17, 2019Updated 7 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- Automatically exported from code.google.com/p/bicubic-interpolation-image-processing☆10Jan 27, 2016Updated 10 years ago
- RISC-V IOMMU in verilog☆22Jun 18, 2022Updated 4 years ago
- 4096bit Iterative digit-digit Montgomery Multiplication in Verilog☆20Apr 18, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- IOPMP IP☆27Jul 11, 2025Updated last year
- Generate SystemVerilog/UVM block level testbench setup with python script☆11Oct 3, 2017Updated 9 years ago
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 5 years ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆34Feb 6, 2020Updated 6 years ago
- kcf tracker of FPGA Accelerate☆10Jul 20, 2017Updated 9 years ago
- NeoPixel LED Controller | NeoPixel LED 控制器 | 基於MAX10 FPGA的音樂全彩光立方LED控制器☆12Jan 4, 2022Updated 4 years ago
- Maven Silicon Project☆20Oct 13, 2018Updated 8 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 6 years ago
- Designed a closed page policy memory controller following the timing specifications for DDR3 DRAM in system verilog. Was responsible for …☆11Mar 4, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- AMBA 3 AHB UVM TB☆35Mar 21, 2019Updated 7 years ago
- ☆13Oct 23, 2022Updated 4 years ago
- ☆22May 18, 2018Updated 8 years ago
- VisionGRU: A Linear-Complexity RNN Model for Efficient Image Analysis☆14Dec 26, 2024Updated last year
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated 2 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 8 years ago
- Tools for FPGA Assurance Flows☆14Sep 25, 2026Updated last month
- small tools developed at work☆10Aug 25, 2026Updated 2 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 11 years ago
- 小鹅通下载自己订阅的视频,方便离线观看☆14Nov 10, 2023Updated 2 years ago
- A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs☆11Jun 19, 2020Updated 6 years ago
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 10 years ago
- Input / Output Physical Memory Protection Unit for RISC-V☆17Jul 20, 2023Updated 3 years ago
- Verilog-Based-NoC-Simulator☆12May 4, 2016Updated 10 years ago
- RTL and UVM test code of a Multi-NoC system☆12Dec 7, 2021Updated 4 years ago
- ☆29Updated this week
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 12 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A python project to automatically generate the UVM testbench document.☆21Feb 27, 2024Updated 2 years ago
- BiSUNA framework specialized to compile for the Xilinx Alveo U50☆13Dec 3, 2020Updated 5 years ago
- Advanced Peripheral Bus (APB) UVM testbench project☆10Apr 9, 2017Updated 9 years ago
- Formulated testbench using System Verilog and UVM and verified I2C bus controller with APB interface☆15Dec 8, 2020Updated 5 years ago
- ☆44May 3, 2026Updated 6 months ago
- Generate UVM testbench framework template files with Python 3☆26Dec 23, 2019Updated 6 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago