Nuclei-Software / e603_hbirdLinks
RV64GC Linux Capable RISC-V Core
☆44Updated last month
Alternatives and similar repositories for e603_hbird
Users that are interested in e603_hbird are comparing it to the libraries listed below
Sorting:
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆29Updated last week
- DUTH RISC-V Superscalar Microprocessor☆32Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆44Updated 2 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆15Updated 3 weeks ago
- Basic floating-point components for RISC-V processors☆67Updated 5 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.☆25Updated last week
- Chisel implementation of Neural Processing Unit for System on the Chip☆23Updated 3 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆71Updated last year
- ☆32Updated last week
- PCI Express controller model☆69Updated 3 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- ☆57Updated 6 years ago
- ☆30Updated 8 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 4 months ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- matrix-coprocessor for RISC-V☆25Updated 7 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated last week
- Unit tests generator for RVV 1.0☆95Updated 3 weeks ago
- ☆37Updated 7 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆31Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last week
- A simple, scalable, source-synchronous, all-digital DDR link☆31Updated last week