Alternatives and similar repositories for trinity

Users that are interested in trinity are comparing it to the libraries listed below

• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆53Updated 3 years ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆30Updated 3 years ago
• OSCPU / ysyxSoC
  ☆89Updated last month
• OSCPU / yosys-sta
  ☆84Updated 6 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆69Updated last year
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆43Updated 2 years ago
• pulp-platform / fpu
  ☆56Updated 6 years ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆69Updated last year
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆72Updated this week
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆27Updated this week
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆121Updated 8 months ago
• OSCPU / chisel-playground
  ☆68Updated 9 months ago
• OpenXiangShan / GEM5
  ☆111Updated this week
• lizhirui / DreamCore
  ☆64Updated 3 years ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated 5 months ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆44Updated 2 years ago
• RoyanTuscano / -TAGE-based-Predictor-Verilog-Code
  Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
  ☆21Updated 7 years ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆25Updated 5 months ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆70Updated 2 years ago
• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆55Updated last year
• arch-simulator-sig / simulator-paper
  ☆11Updated last year
• pulp-platform / ITA
  ☆54Updated 6 months ago
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆26Updated 2 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆45Updated 3 years ago
• meton-robean / ResearchNote
  通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …
  ☆77Updated 5 years ago