Alternatives and similar repositories for trinity:

Users that are interested in trinity are comparing it to the libraries listed below

• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 11 months ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• OSCPU / chisel-playground
  ☆64Updated 3 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆50Updated 2 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆49Updated last week
• OSCPU / yosys-sta
  ☆63Updated 2 weeks ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆27Updated 3 years ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 3 weeks ago
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆24Updated last week
• OSCPU / ysyxSoC
  ☆86Updated this week
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 9 months ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 2 months ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆35Updated 2 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆59Updated last year
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆18Updated 4 months ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆30Updated 3 months ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆23Updated last year
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆53Updated 3 years ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆14Updated 2 years ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆18Updated 2 months ago
• MrAMS / NagiCore
  顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel
  ☆19Updated 5 months ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆61Updated last year
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆20Updated last week
• XS-MLVP / toffee
  A framework for building hardware verification platform using software method
  ☆18Updated last week
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• aaronshappell / tage-predictor
  SystemVerilog implemention of the TAGE branch predictor
  ☆12Updated 3 years ago
• XS-MLVP / UnityChipForXiangShan
  Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor
  ☆35Updated last week