ZipCPU / axidmacheck
AXI DMA Check: A utility to measure DMA speeds in simulation
☆12Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for axidmacheck
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆9Updated last year
- WISHBONE Interconnect☆11Updated 7 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆10Updated 4 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆13Updated 3 months ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 3 years ago
- SystemVerilog Logger☆16Updated 2 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆12Updated 9 years ago
- DMA core compatible with AHB3-Lite☆10Updated 5 years ago
- APB Logic☆12Updated 9 months ago
- ☆16Updated 5 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆10Updated 3 weeks ago
- Python/Simulator integration using procedure calls☆9Updated 4 years ago
- ☆20Updated 5 years ago
- CORE-V MCU UVM Environment and Test Bench☆17Updated 4 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆12Updated 9 months ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆12Updated 5 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- File editor for the Xilinx AXI Traffic Generator IP☆15Updated last year
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆17Updated 6 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆11Updated 9 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆15Updated 4 years ago
- verification of simple axi-based cache☆17Updated 5 years ago
- Generate UVM testbench framework template files with Python 3☆21Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Verification IP for UART protocol☆15Updated 4 years ago
- Groundhog - Serial ATA Host Bus Adapter☆21Updated 6 years ago
- Common SystemVerilog RTL modules for RgGen☆11Updated 6 months ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- Python tools for processing Verilog files☆10Updated 12 years ago