Alternatives and similar repositories for YuQuan

Users that are interested in YuQuan are comparing it to the libraries listed below

• pulp-platform / dram_rtl_sim
  ☆17Updated 4 months ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆33Updated last week
• ucb-bar / radiance
  A Heterogeneous GPU Platform for Chipyard SoC
  ☆42Updated this week
• XS-MLVP / Example-NutShellCache
  开放验证平台NutShell Cache验证案例
  ☆11Updated 2 months ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆46Updated 3 weeks ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆77Updated 2 years ago
• PrincetonUniversity / maple
  MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeli…
  ☆21Updated last year
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆26Updated 3 weeks ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆32Updated 3 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆39Updated 4 years ago
• pulp-platform / fpu
  ☆58Updated 6 years ago
• yonseicasl / NPUsim
  NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators
  ☆46Updated last year
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆62Updated 4 years ago
• pku-liang / ksim
  ☆52Updated last year
• chipsalliance / aib-protocols
  ☆29Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 2 months ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆31Updated last month
• sequencer / arithmetic
  ☆33Updated 10 months ago
• OSCPU / chisel-playground
  ☆71Updated last week
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆29Updated 4 years ago
• RISMicroDevices / RMM4NC30F2X
  Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
  ☆11Updated 3 years ago
• mohsaied / rtl2booksim
  Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.
  ☆25Updated 10 years ago
• Nuclei-Software / e603_hbird
  RV64GC Linux Capable RISC-V Core
  ☆52Updated 3 months ago
• pulp-platform / axi_llc
  ☆33Updated 2 months ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆82Updated 2 months ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆48Updated this week
• pulp-platform / quadrilatero
  matrix-coprocessor for RISC-V
  ☆30Updated 2 months ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆22Updated 6 years ago