EDAPack / edapack
Provides a packaged collection of open source EDA tools
☆12Updated 5 years ago
Alternatives and similar repositories for edapack:
Users that are interested in edapack are comparing it to the libraries listed below
- LibreSilicon's Standard Cell Library Generator☆18Updated 10 months ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆13Updated 8 years ago
- Benchmarks for Yosys development☆23Updated 5 years ago
- KLayout technology files for ASAP7 FinFET educational process☆20Updated 2 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 8 months ago
- ☆20Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆40Updated last year
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- Synthesiser for Asynchronous Verilog Language☆19Updated 10 years ago
- tools regarding on analog modeling, validation, and generation☆22Updated last year
- ☆43Updated 5 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- ☆36Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆36Updated 3 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆19Updated 3 years ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆25Updated 4 months ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated 2 weeks ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆30Updated 4 years ago
- Benchmarks for High-Level Synthesis☆10Updated 2 years ago
- ☆22Updated last year
- ☆17Updated 5 months ago
- Hardware Formal Verification☆15Updated 4 years ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆13Updated 4 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆22Updated 3 months ago
- OpenSoC Fabric - A Network-On-Chip Generator☆17Updated 7 years ago