Provides a packaged collection of open source EDA tools
☆12Apr 14, 2019Updated 7 years ago
Alternatives and similar repositories for edapack
Users that are interested in edapack are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆44Jan 26, 2020Updated 6 years ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆12Dec 27, 2020Updated 5 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Dec 1, 2018Updated 7 years ago
- ☆33Jan 24, 2020Updated 6 years ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 8 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Analyzer and simulator of logic circuit☆15May 8, 2017Updated 9 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆34Updated this week
- Synchronous FIFOs designed in Verilog/System Verilog.☆25Dec 21, 2025Updated 7 months ago
- ☆20Mar 1, 2021Updated 5 years ago
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 9 years ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- Robot Framework KiCad Library☆10Oct 20, 2022Updated 3 years ago
- ☆103Jun 26, 2019Updated 7 years ago
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 11 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A collection of big designs to run post-synthesis simulations with yosys☆51Oct 27, 2015Updated 10 years ago
- BAG (BAG AMS Generator) Primitives Library for SKY130☆22May 16, 2023Updated 3 years ago
- Next-Generation FPGA Place-and-Route☆10Aug 1, 2018Updated 8 years ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Dec 15, 2020Updated 5 years ago
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 7 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆24Sep 26, 2024Updated last year
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- Hardware Trojan on a Basis 3 FPGA for Hardware and Embedded Systems Security☆11May 1, 2017Updated 9 years ago
- RISC-V BSV Specification☆24Apr 28, 2026Updated 3 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A reconfigurable logic circuit made of identical rotatable tiles.☆26Nov 15, 2021Updated 4 years ago
- SCARV: a side-channel hardened RISC-V platform☆23Mar 31, 2021Updated 5 years ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆38Mar 7, 2026Updated 5 months ago
- EDA Analytics Central☆16Dec 8, 2022Updated 3 years ago
- Used for hardware trojan detection（Based on Trust_Hub）☆10Jul 30, 2019Updated 7 years ago
- ☆31Aug 19, 2019Updated 6 years ago
- Morphle Logic V1.0, an open hardware asynchronous runtime reconfigurable array ARRA or PPL,FPGA,CPLD☆26Feb 12, 2023Updated 3 years ago
- Free open source EDA tools☆66Oct 1, 2019Updated 6 years ago
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆17May 23, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆266Jul 22, 2026Updated 2 weeks ago
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated 5 months ago
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated last year
- GUI for SymbiYosys☆18Updated this week
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- DOULOS Easier UVM Code Generator☆37May 6, 2017Updated 9 years ago
- A copy of the latest version of MVSIS☆13Apr 18, 2021Updated 5 years ago