Alternatives and similar repositories for litex_vexriscv_smp_test:

Users that are interested in litex_vexriscv_smp_test are comparing it to the libraries listed below

• whitequark / Yumewatari
  妖刀夢渡
  ☆59Updated 5 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆56Updated last month
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated last week
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆38Updated last year
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆30Updated 4 years ago
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 4 years ago
• olofk / observer
  ☆41Updated 4 years ago
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 6 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• Domipheus / ArtyS7-RPU-SoC
  Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.
  ☆39Updated 4 years ago
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆41Updated 2 months ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆35Updated 5 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• enjoy-digital / litesata_axiom
  ☆12Updated 4 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last week
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆42Updated 11 months ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 3 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆43Updated 2 years ago
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆33Updated 6 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆41Updated last year
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆95Updated last year
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆32Updated 3 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆32Updated 3 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆41Updated 2 months ago
• litex-hub / pythondata-cpu-rocket
  Python module containing verilog files for rocket cpu (for use with LiteX).
  ☆13Updated 2 months ago