bit field diagram renderer
☆391Feb 22, 2024Updated 2 years ago
Alternatives and similar repositories for bitfield
Users that are interested in bitfield are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Digital timing diagram rendering engine☆3,390Apr 3, 2026Updated last month
- HDL symbol generator☆202Feb 2, 2023Updated 3 years ago
- Digital Circuit rendering engine☆39Mar 31, 2026Updated last month
- 🔍 Zoomable Waveform viewer for the Web☆43Nov 3, 2020Updated 5 years ago
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 5 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- datasheet generator☆30Jul 18, 2025Updated 9 months ago
- A sphinx extension that allows including wavedrom diagrams by using its text-based representation☆39Sep 3, 2024Updated last year
- 🔁 elastic circuit toolchain☆33Dec 2, 2024Updated last year
- D3.js and ELK based schematic visualizer☆119Feb 27, 2024Updated 2 years ago
- hardware library for hwt (= ipcore repo)☆44Dec 23, 2025Updated 4 months ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆52Jun 5, 2022Updated 3 years ago
- D3.js based wave (signal) visualizer☆68Aug 19, 2025Updated 8 months ago
- Hardware Description Languages☆1,142Apr 6, 2026Updated 3 weeks ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- ☆27Mar 17, 2026Updated last month
- A Sphinx domain providing VHDL language support.☆21Dec 18, 2023Updated 2 years ago
- CLI for WaveDrom☆69Feb 22, 2024Updated 2 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Aug 20, 2022Updated 3 years ago
- Simplified environment for litex☆14Oct 5, 2020Updated 5 years ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 3 years ago
- Code generation tool for control and status registers☆455Apr 19, 2026Updated 2 weeks ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,829Mar 13, 2026Updated last month
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Dec 26, 2023Updated 2 years ago
- SystemRDL 2.0 language compiler front-end☆277Apr 10, 2026Updated 3 weeks ago
- draws an SVG schematic from a JSON netlist☆789Jan 25, 2024Updated 2 years ago
- An FPGA in your USB Port☆11Jul 1, 2021Updated 4 years ago
- An abstraction library for interfacing EDA tools☆762Apr 24, 2026Updated last week
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆224Dec 23, 2025Updated 4 months ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆504Apr 24, 2026Updated last week
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆258Apr 23, 2026Updated last week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Package manager and build abstraction tool for FPGA/ASIC development☆1,410Feb 13, 2026Updated 2 months ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆826Apr 22, 2026Updated last week
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆14Sep 22, 2025Updated 7 months ago
- Small footprint and configurable HyperBus core☆14Jul 6, 2022Updated 3 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- SystemVerilog linter☆381Nov 6, 2025Updated 5 months ago
- A curated list of awesome resources for HDL design and verification☆173Updated this week