bit field diagram renderer
☆392Feb 22, 2024Updated 2 years ago
Alternatives and similar repositories for bitfield
Users that are interested in bitfield are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Digital timing diagram rendering engine☆3,404Apr 3, 2026Updated last month
- HDL symbol generator☆202Feb 2, 2023Updated 3 years ago
- Digital Circuit rendering engine☆39Mar 31, 2026Updated last month
- 🔍 Zoomable Waveform viewer for the Web☆43Nov 3, 2020Updated 5 years ago
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 6 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- datasheet generator☆30Jul 18, 2025Updated 10 months ago
- A sphinx extension that allows including wavedrom diagrams by using its text-based representation☆39Sep 3, 2024Updated last year
- 🔁 elastic circuit toolchain☆33Dec 2, 2024Updated last year
- D3.js and ELK based schematic visualizer☆119May 13, 2026Updated last week
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆52Jun 5, 2022Updated 3 years ago
- D3.js based wave (signal) visualizer☆68May 13, 2026Updated last week
- Hardware Description Languages☆1,147Apr 6, 2026Updated last month
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆27Mar 17, 2026Updated 2 months ago
- A Sphinx domain providing VHDL language support.☆21Dec 18, 2023Updated 2 years ago
- CLI for WaveDrom☆69Feb 22, 2024Updated 2 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆33Aug 20, 2022Updated 3 years ago
- Simplified environment for litex☆14Oct 5, 2020Updated 5 years ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 3 years ago
- Code generation tool for control and status registers☆455Apr 19, 2026Updated last month
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,846Mar 13, 2026Updated 2 months ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Dec 26, 2023Updated 2 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- SystemRDL 2.0 language compiler front-end☆278Apr 10, 2026Updated last month
- An FPGA in your USB Port☆11Jul 1, 2021Updated 4 years ago
- draws an SVG schematic from a JSON netlist☆792Jan 25, 2024Updated 2 years ago
- An abstraction library for interfacing EDA tools☆770Apr 24, 2026Updated 3 weeks ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆225May 13, 2026Updated last week
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆510May 12, 2026Updated last week
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆258May 15, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,417May 10, 2026Updated last week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- VUnit is a unit testing framework for VHDL/SystemVerilog☆826May 14, 2026Updated last week
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆14Sep 22, 2025Updated 8 months ago
- Small footprint and configurable HyperBus core☆14Jul 6, 2022Updated 3 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- SystemVerilog linter☆383Nov 6, 2025Updated 6 months ago
- A curated list of awesome resources for HDL design and verification☆174Updated this week
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago