Alternatives and similar repositories for wavedrom.github.io:

Users that are interested in wavedrom.github.io are comparing it to the libraries listed below

• wavedrom / wavedrom
  Digital timing diagram rendering engine
  ☆3,046Updated this week
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆727Updated 3 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆571Updated 6 months ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆587Updated last week
• analogdevicesinc / hdl
  HDL libraries and projects
  ☆1,570Updated this week
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,254Updated this week
• Digilent / vivado-library
  ☆596Updated 7 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,188Updated last week
• KastnerRG / riffa
  The RIFFA development repository
  ☆796Updated 7 months ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,240Updated 8 months ago
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,022Updated last week
• wavedrom / bitfield
  bit field diagram renderer
  ☆352Updated 11 months ago
• Nitcloud / Digital-IDE
  在vscode上的数字设计开发插件
  ☆348Updated 2 years ago
• cocotb / cocotb
  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
  ☆1,871Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,474Updated this week
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,360Updated this week
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,234Updated 7 months ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,345Updated 2 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆513Updated last week
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆670Updated 7 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,235Updated 2 weeks ago
• slaclab / surf
  A huge VHDL library for FPGA development
  ☆368Updated this week
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆563Updated 4 years ago
• Digilent / vivado-boards
  ☆414Updated 3 weeks ago
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆695Updated 2 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆560Updated 2 weeks ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,004Updated 6 months ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆412Updated 2 years ago
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆758Updated this week
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆856Updated 3 years ago