Alternatives and similar repositories for systemrdl-compiler:

Users that are interested in systemrdl-compiler are comparing it to the libraries listed below

• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆198Updated 4 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆309Updated this week
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆250Updated last month
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆382Updated 2 weeks ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆244Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆268Updated this week
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆119Updated last week
• pyuvm / pyuvm
  The UVM written in Python
  ☆414Updated 2 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆173Updated 3 months ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆373Updated last month
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆590Updated this week
• svunit / svunit
  ☆196Updated 2 weeks ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆109Updated last year
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆171Updated 2 years ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆212Updated last week
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆428Updated 2 weeks ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆135Updated last month
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆127Updated last year
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆236Updated 4 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆559Updated last week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆115Updated last week
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆128Updated 9 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆460Updated last month
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆276Updated 5 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆400Updated 6 months ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆267Updated 2 weeks ago
• raysalemi / Python4RTLVerification
  ☆150Updated 2 years ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆289Updated last week
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆81Updated 3 years ago
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆205Updated last week