Alternatives and similar repositories for wishbone:

Users that are interested in wishbone are comparing it to the libraries listed below

• VHDL / news
  VHDL related news.
  ☆25Updated this week
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆47Updated this week
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 2 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated last month
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆24Updated 10 months ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆27Updated last year
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆29Updated last month
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 6 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆54Updated 4 years ago
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆23Updated 5 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆41Updated last year
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated last month
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆58Updated last week
• VHDL / CoreLib
  A VHDL Core Library.
  ☆17Updated 7 years ago
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆14Updated 5 years ago
• mattvenn / gtkwave-python-filter-process
  ☆33Updated 4 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆26Updated 2 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆43Updated this week
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆58Updated last week
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated last week
• nobodywasishere / vhdlref
  A usable language reference for VHDL that is concise, direct, and easy to understand.
  ☆25Updated last year
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 3 months ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• edaa-org / pyEDAA.Reports
  Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
  ☆14Updated this week
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago