Alternatives and similar repositories for wishbone

Users that are interested in wishbone are comparing it to the libraries listed below

• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated last week
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated last year
• VHDL / news
  VHDL related news.
  ☆27Updated this week
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆82Updated last month
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆64Updated 4 years ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆32Updated 3 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆34Updated 3 weeks ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆82Updated last week
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆32Updated last year
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆75Updated last week
• nobodywasishere / vhdlref
  A usable language reference for VHDL that is concise, direct, and easy to understand.
  ☆26Updated 4 months ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆62Updated 2 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆48Updated 2 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆61Updated 2 weeks ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 7 months ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆27Updated last year
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆22Updated 2 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆74Updated last year
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆46Updated last week
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆51Updated last month
• miree / gvi
  GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
  ☆16Updated 9 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 6 months ago
• CESNET / sphinx-vhdl
  ☆24Updated 10 months ago