π₯ Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
β33Aug 20, 2022Updated 3 years ago
Alternatives and similar repositories for fpga_torture
Users that are interested in fpga_torture are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ZX80/81 implementation for the Ulx3sβ12May 4, 2022Updated 4 years ago
- β10Oct 23, 2016Updated 9 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.β14Jul 20, 2026Updated last week
- a project to check the FOSS synthesizers against vendors EDA toolsβ12Sep 26, 2020Updated 5 years ago
- VHDL String Formatting Libraryβ27Apr 27, 2024Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI β’ AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Example of Test Driven Design with VUnitβ16Nov 22, 2021Updated 4 years ago
- Library of reusable VHDL componentsβ28Mar 7, 2024Updated 2 years ago
- VHDL package to provide C-like string formattingβ15May 6, 2022Updated 4 years ago
- Interfacing VHDL and foreign languages with VUnitβ15Feb 20, 2020Updated 6 years ago
- An open-source VHDL library for FPGA design.β32Jun 2, 2022Updated 4 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)β69Feb 16, 2026Updated 5 months ago
- A translation of the Xilinx XPM library to VHDL for simulation purposesβ70Updated this week
- Examples and design pattern for VHDL verificationβ15Apr 10, 2016Updated 10 years ago
- VHDL related news.β27Updated this week
- Simple, predictable pricing with DigitalOcean hosting β’ AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workβ¦β10Jan 13, 2022Updated 4 years ago
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.β82Jun 21, 2026Updated last month
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boardsβ48Feb 12, 2026Updated 5 months ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 featuresβ32Jan 30, 2025Updated last year
- A usable language reference for VHDL that is concise, direct, and easy to understand.β26Jun 23, 2026Updated last month
- TI-99/4A FPGA implementation for the Icestorm toolchainβ22Nov 29, 2025Updated 8 months ago
- A bit-serial CPUβ20Sep 29, 2019Updated 6 years ago
- Standard and Curated cores, tested and working.β11Dec 29, 2022Updated 3 years ago
- Specification of the Wishbone SoC Interconnect Architectureβ54Jun 5, 2022Updated 4 years ago
- Open source password manager - Proton Pass β’ AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Trying to verify Verilog/VHDL designs with formal methods and toolsβ43Mar 7, 2024Updated 2 years ago
- β14Aug 25, 2019Updated 6 years ago
- VHDLproc is a VHDL preprocessorβ24May 12, 2022Updated 4 years ago
- VHDL dependency analyzerβ25Mar 10, 2020Updated 6 years ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.β14Sep 22, 2025Updated 10 months ago
- Experiments with Cologne Chip's GateMate FPGA architectureβ19Nov 16, 2023Updated 2 years ago
- SNES for MiSTerβ16Sep 5, 2025Updated 10 months ago
- KiCad RF Stuffβ14Aug 17, 2021Updated 4 years ago
- CLI tool for RTL design space exploration on top of Vivadoβ15Jun 5, 2023Updated 3 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer β’ AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Rust proof-of-concept for GPU waveform renderingβ13Jul 22, 2020Updated 6 years ago
- Documenting Lattice's 28nm FPGA partsβ153Jul 19, 2026Updated last week
- Fixed-point math library with VHDL, Python and MATLAB supportβ39Apr 13, 2026Updated 3 months ago
- CologneChip GateMate FPGA Module: GMM-7550β36Jan 17, 2026Updated 6 months ago
- β12Jun 4, 2021Updated 5 years ago
- JavaScript action for users to easily install tip/nightly GHDL assets in GitHub Actions workflowsβ16Jan 12, 2025Updated last year
- nMigen examples for the ULX3S boardβ16Nov 30, 2020Updated 5 years ago