🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
☆32Aug 20, 2022Updated 3 years ago
Alternatives and similar repositories for fpga_torture
Users that are interested in fpga_torture are comparing it to the libraries listed below
Sorting:
- ☆10Oct 23, 2016Updated 9 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Nov 16, 2023Updated 2 years ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆35Feb 25, 2026Updated last week
- VHDL String Formatting Library☆27Apr 27, 2024Updated last year
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 3 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Feb 24, 2026Updated last week
- ☆12Aug 25, 2019Updated 6 years ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆64Nov 7, 2025Updated 4 months ago
- CologneChip GateMate FPGA Module: GMM-7550☆28Jan 17, 2026Updated last month
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- Example of Test Driven Design with VUnit☆16Nov 22, 2021Updated 4 years ago
- VHDL related news.☆27Mar 2, 2026Updated last week
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 9 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Feb 16, 2026Updated 2 weeks ago
- SNES for MiSTer☆16Sep 5, 2025Updated 6 months ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- A bit-serial CPU☆20Sep 29, 2019Updated 6 years ago
- TI-99/4A FPGA implementation for the Icestorm toolchain☆20Nov 29, 2025Updated 3 months ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆13Sep 22, 2025Updated 5 months ago
- A robust, open-source physical layer implementation for FPGA-to-FPGA communication over high-speed serial links of the Quantum Error Corr…☆28Mar 2, 2026Updated last week
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆76Mar 1, 2026Updated last week
- VHDL dependency analyzer☆24Mar 10, 2020Updated 5 years ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 3 years ago
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆26Sep 16, 2025Updated 5 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆47Feb 12, 2026Updated 3 weeks ago
- ☆25Jan 16, 2019Updated 7 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- vhdl related contents☆11Apr 27, 2020Updated 5 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆52Jun 5, 2022Updated 3 years ago
- Conway's Game of Life implemented with the Linux framebuffer☆10Dec 28, 2014Updated 11 years ago
- Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.☆10Jul 22, 2020Updated 5 years ago
- Standard and Curated cores, tested and working.☆11Dec 29, 2022Updated 3 years ago
- VUnit and Cocotb Smashed Together☆15May 31, 2024Updated last year
- Rust proof-of-concept for GPU waveform rendering☆13Jul 22, 2020Updated 5 years ago
- TLUT tool flow for parameterised configurations for FPGAs☆16Aug 5, 2024Updated last year
- Unified Coverage Interoperability Standard (UCIS)☆14Jan 28, 2026Updated last month