Alternatives and similar repositories for sphinx-wavedrom

Users that are interested in sphinx-wavedrom are comparing it to the libraries listed below

• wallento / wavedrompy
  WaveDrom compatible python command line
  ☆108Updated 2 years ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆16Updated 9 years ago
• witchard / nbwavedrom
  A simple function to add wavedrom diagrams into an ipython notebook.
  ☆24Updated 3 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆78Updated 3 years ago
• VHDL / VHDLDomain
  A Sphinx domain providing VHDL language support.
  ☆21Updated last year
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆61Updated 2 months ago
• SanDisk-Open-Source / pyvcd
  Python package for writing Value Change Dump (VCD) files.
  ☆122Updated 9 months ago
• edaa-org / IPXACT-Schema
  This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.
  ☆19Updated 3 months ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated 2 years ago
• edaa-org / pyEDAA.Reports
  Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
  ☆14Updated this week
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆46Updated 3 years ago
• davidthings / hdelk
  Web-based HDL diagramming tool
  ☆79Updated 2 years ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆61Updated last year
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆21Updated 2 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 3 years ago
• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated 3 weeks ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆55Updated last month
• suoto / fpga_cores
  ☆32Updated 2 years ago
• wavedrom / datasheet
  datasheet generator
  ☆28Updated last month
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆24Updated 5 years ago
• LaurentCabaret / pyVhdl2Sch
  pyVhdl2sch is a python based VHDL to (pdf) schematic converter
  ☆33Updated 5 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆45Updated last week
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆64Updated 2 weeks ago
• VHDL / news
  VHDL related news.
  ☆25Updated this week
• NJDFan / register-maps
  Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.
  ☆13Updated 3 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated 4 months ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆26Updated 6 months ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated last month