drom / logidrom
Digital Circuit rendering engine
☆36Updated last year
Alternatives and similar repositories for logidrom:
Users that are interested in logidrom are comparing it to the libraries listed below
- Extensible FPGA control platform☆55Updated last year
- mantle library☆42Updated 2 years ago
- 🔍 Zoomable Waveform viewer for the Web☆42Updated 4 years ago
- Wishbone interconnect utilities☆38Updated 7 months ago
- Verification Utilities for MyHDL☆17Updated last year
- 🕒 Static Timing Analysis diagram renderer☆13Updated last year
- A simple function to add wavedrom diagrams into an ipython notebook.☆22Updated 3 years ago
- FuseSoc Verification Automation☆22Updated 2 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- ☆31Updated last year
- sample VCD files☆36Updated 11 months ago
- GUI editor for hardware description designs☆27Updated last year
- Small footprint and configurable Inter-Chip communication cores☆54Updated last week
- A padring generator for ASICs☆24Updated last year
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆16Updated 5 years ago
- Reusable Verilog 2005 components for FPGA designs☆39Updated last year
- Sphinx Extension which generates various types of diagrams from Verilog code.☆56Updated last year
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆47Updated this week
- LunaPnR is a place and router for integrated circuits☆45Updated last month
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- A collection of debugging busses developed and presented at zipcpu.com☆37Updated last year
- ☆22Updated last year
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- ☆29Updated 3 years ago
- VHDL dependency analyzer☆23Updated 4 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 6 months ago
- 👾 Design ∪ Hardware☆72Updated 2 months ago
- A tool for merging the MyHDL workflow with Vivado☆19Updated 4 years ago