drom / logidromLinks
Digital Circuit rendering engine
☆39Updated last year
Alternatives and similar repositories for logidrom
Users that are interested in logidrom are comparing it to the libraries listed below
Sorting:
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆35Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆58Updated last week
- GUI editor for hardware description designs☆28Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆43Updated 3 months ago
- mantle library☆44Updated 2 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- 🔍 Zoomable Waveform viewer for the Web☆43Updated 4 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 2 years ago
- FuseSoc Verification Automation☆22Updated 2 years ago
- Verification Utilities for MyHDL☆17Updated last year
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆88Updated 6 years ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆60Updated last year
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- sample VCD files☆37Updated last year
- A tool for merging the MyHDL workflow with Vivado☆20Updated 5 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆44Updated last week
- Featherweight RISC-V implementation☆52Updated 3 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- Simple Python parser for extracting HDL (VHDL or Verilog) documentation☆21Updated last year
- A padring generator for ASICs☆25Updated 2 years ago
- ☆35Updated 6 months ago
- IRSIM switch-level simulator for digital circuits☆34Updated last month
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated last week
- Virtual development board for HDL design☆42Updated 2 years ago
- ☆36Updated 2 years ago