Alternatives and similar repositories for zoom

Users that are interested in zoom are comparing it to the libraries listed below

• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆45Updated 3 years ago
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆44Updated last week
• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated last year
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated last year
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆48Updated this week
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated last year
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆21Updated 2 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• pieter3d / simview
  ☆79Updated last year
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆62Updated last year
• eine / hwd-ide
  ☆20Updated 5 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆53Updated last month
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆42Updated this week
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• wavedrom / vcd-samples
  sample VCD files
  ☆37Updated last year
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• VHDL / news
  VHDL related news.
  ☆25Updated this week
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆42Updated last week
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆52Updated this week
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 4 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 3 months ago
• wavedrom / datasheet
  datasheet generator
  ☆28Updated 2 weeks ago
• olofk / observer
  ☆41Updated 5 years ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆25Updated last year
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆61Updated last week
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago