wavedrom / zoom
🔍 Zoomable Waveform viewer for the Web
☆42Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for zoom
- Digital Circuit rendering engine☆35Updated last year
- Python script to transform a VCD file to wavedrom format☆74Updated 2 years ago
- Using ModelSim Foreign Language Interface for c – VHDL Co-Simulation and for Simulator Control on Linux x86 Platform☆26Updated 3 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated 8 months ago
- 👾 Design ∪ Hardware☆72Updated 2 weeks ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆64Updated 2 months ago
- A padring generator for ASICs☆22Updated last year
- FuseSoc Verification Automation☆21Updated 2 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆30Updated 2 months ago
- Extensible FPGA control platform☆54Updated last year
- A simple function to add wavedrom diagrams into an ipython notebook.☆22Updated 2 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆46Updated this week
- Specification of the Wishbone SoC Interconnect Architecture☆41Updated 2 years ago
- Web-based HDL diagramming tool☆73Updated last year
- ☆30Updated last year
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆29Updated this week
- ☆26Updated last year
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆76Updated 4 years ago
- SVA examples and demonstration☆16Updated 4 years ago
- ☆76Updated 8 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆47Updated 2 months ago
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆52Updated last week
- sample VCD files☆36Updated 9 months ago
- Wishbone interconnect utilities☆37Updated 6 months ago
- D3.js based wave (signal) visualizer☆59Updated 10 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆62Updated last year