Alternatives and similar repositories for zoom

Users that are interested in zoom are comparing it to the libraries listed below

• davidthings / hdelk
  Web-based HDL diagramming tool
  ☆81Updated 2 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆48Updated 3 years ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated 4 months ago
• ghdl / docker
  Scripts to build and use docker images including GHDL
  ☆43Updated last year
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆46Updated last week
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆31Updated 3 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• wavedrom / cli
  CLI for WaveDrom
  ☆63Updated last year
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆83Updated 5 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆52Updated 2 years ago
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆79Updated 3 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆21Updated 2 years ago
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 3 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• pieter3d / simview
  ☆88Updated last month
• eine / hwd-ide
  ☆20Updated 5 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 10 months ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• VHDL / news
  VHDL related news.
  ☆27Updated this week
• andrepool / fli
  Using ModelSim Foreign Language Interface for c – VHDL Co-Simulation and for Simulator Control on Linux x86 Platform
  ☆28Updated 4 years ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆26Updated last year
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆32Updated 10 months ago
• drom / sta
  🕒 Static Timing Analysis diagram renderer
  ☆13Updated last year
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆58Updated 2 weeks ago