wavedrom / zoomLinks
🔍 Zoomable Waveform viewer for the Web
☆44Updated 4 years ago
Alternatives and similar repositories for zoom
Users that are interested in zoom are comparing it to the libraries listed below
Sorting:
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- Web-based HDL diagramming tool☆79Updated 2 years ago
- Python script to transform a VCD file to wavedrom format☆78Updated 2 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆48Updated this week
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 6 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- Scripts to build and use docker images including GHDL☆41Updated 8 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated this week
- Virtual development board for HDL design☆42Updated 2 years ago
- CLI for WaveDrom☆63Updated last year
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated 2 years ago
- Digital Circuit rendering engine☆39Updated last week
- A padring generator for ASICs☆25Updated 2 years ago
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- VHDL String Formatting Library☆25Updated last year
- ☆79Updated last year
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆80Updated 5 years ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- D3.js based wave (signal) visualizer☆63Updated last year
- VHDL related news.☆25Updated this week
- Streaming based VHDL parser.☆84Updated last year
- sample VCD files☆37Updated 3 weeks ago
- A JSON library implemented in VHDL.☆79Updated 2 years ago
- Generate address space documentation HTML from compiled SystemRDL input☆56Updated last month
- Library of reusable VHDL components☆28Updated last year
- Simple parser for extracting VHDL documentation☆71Updated last year
- An abstract language model of VHDL written in Python.☆55Updated last month
- Python package for writing Value Change Dump (VCD) files.☆122Updated 8 months ago
- Verilog wishbone components☆117Updated last year
- Building and deploying container images for open source electronic design automation (EDA)☆115Updated 10 months ago