NJDFan / register-mapsLinks
Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.
☆13Updated 2 months ago
Alternatives and similar repositories for register-maps
Users that are interested in register-maps are comparing it to the libraries listed below
Sorting:
- A VHDL Core Library.☆18Updated 8 years ago
- VHDL related news.☆27Updated this week
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated this week
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- Unified Coverage Interoperability Standard (UCIS)☆13Updated last week
- Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.☆10Updated 5 years ago
- VHDL dependency analyzer☆24Updated 5 years ago
- VHDL String Formatting Library☆26Updated last year
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Updated 3 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Updated 2 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆50Updated 3 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Updated 10 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- VHDL plugin for RgGen☆13Updated 2 weeks ago
- Open Source Verification Bundle for VHDL and System Verilog☆48Updated last year
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆27Updated last month
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Generator for VHDL regular expression matchers☆15Updated 4 years ago
- Interface definitions for VHDL-2019.☆34Updated last week
- Interfacing VHDL and foreign languages with VUnit☆15Updated 5 years ago
- ☆24Updated 8 months ago
- Library of reusable VHDL components☆28Updated last year
- Standard and Curated cores, tested and working.☆11Updated 2 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆31Updated 3 years ago
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.☆16Updated 8 months ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- Example of Test Driven Design with VUnit☆16Updated 4 years ago
- IP-XACT XML binding library☆16Updated 9 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 10 months ago
- TCL framework to package Vivado IP-Cores☆14Updated 3 years ago