walkieq / RNN_HLS
An LSTM template and a few examples using Vivado HLS
☆44Updated 9 months ago
Alternatives and similar repositories for RNN_HLS:
Users that are interested in RNN_HLS are comparing it to the libraries listed below
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆55Updated 3 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆22Updated 5 years ago
- Verilog implementation of Softmax function☆56Updated 2 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 5 months ago
- ☆71Updated 2 years ago
- Hardware accelerator for convolutional neural networks☆36Updated 2 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆22Updated 3 years ago
- ☆56Updated 4 years ago
- ☆60Updated 6 years ago
- CNN Accelerator in Frequency Domain☆12Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆48Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆84Updated 4 years ago
- ☆33Updated 5 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- Library of approximate arithmetic circuits☆53Updated 2 years ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 3 years ago
- Open-source of MSD framework☆16Updated last year
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆13Updated 11 months ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆17Updated 6 years ago
- ☆100Updated 4 years ago