Alternatives and similar repositories for RNN_HLS

Users that are interested in RNN_HLS are comparing it to the libraries listed below

• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆59Updated 3 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago
• awai54st / LUTNet
  ☆59Updated 5 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆68Updated 6 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆35Updated 6 years ago
• AlexMontgomerie / fpgaconvnet-model
  Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
  ☆30Updated 11 months ago
• lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
  This project implements a convolution kernel based on vivado HLS on zcu104
  ☆37Updated 5 years ago
• sherylll / lenet5-accelerator
  FPGA and GPU acceleration of LeNet5
  ☆34Updated 6 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆88Updated 5 years ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆34Updated 6 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆208Updated last week
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆45Updated last year
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆93Updated 4 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• Yang-YiFan / DiracDeltaNet
  PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
  ☆32Updated 6 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆70Updated 3 years ago
• jonathan93sh / CNNA
  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
  ☆26Updated 3 years ago
• mohdumar644 / TinyYOLO-BNN
  Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.
  ☆31Updated 6 years ago
• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆53Updated 7 years ago
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆55Updated 3 years ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆91Updated 3 years ago
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆52Updated last year
• WenqiJiang / FPGA-Based-RNN-Accelerator-Using-Vivado-HLS
  This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …
  ☆23Updated 6 years ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆99Updated last year
• AlexMontgomerie / fpgaconvnet-hls
  ☆32Updated 11 months ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆48Updated 7 months ago
• williamyang4978 / PipeCNN_Winograd
  An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
  ☆38Updated 4 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• PSCLab-ASU / Systolic-CNN
  ☆17Updated 4 years ago