walkieq / RNN_HLSView external linksLinks
An LSTM template and a few examples using Vivado HLS
☆47May 4, 2024Updated last year
Alternatives and similar repositories for RNN_HLS
Users that are interested in RNN_HLS are comparing it to the libraries listed below
Sorting:
- SAMO: Streaming Architecture Mapping Optimisation☆34Oct 4, 2023Updated 2 years ago
- FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks.☆27Aug 15, 2023Updated 2 years ago
- ☆22Sep 27, 2022Updated 3 years ago
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆16Dec 29, 2024Updated last year
- ☆18Jan 22, 2025Updated last year
- ☆16Oct 29, 2021Updated 4 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆32Nov 7, 2024Updated last year
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆97Oct 2, 2021Updated 4 years ago
- Fast inference of Boosted Decision Trees in FPGAs☆57Jan 28, 2026Updated 2 weeks ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆97Jan 29, 2026Updated 2 weeks ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Mar 17, 2022Updated 3 years ago
- ☆10Nov 5, 2019Updated 6 years ago
- ☆65May 6, 2020Updated 5 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆24Jun 28, 2019Updated 6 years ago
- Generate an FPGA design for a TWN☆10Nov 4, 2019Updated 6 years ago
- muSYCL, the SYCL musical!☆13Aug 25, 2024Updated last year
- ☆31Nov 7, 2024Updated last year
- Vitis HLS Library for FINN☆214Jan 9, 2026Updated last month
- An implementation of a BinaryConnect network for cifar10☆11Nov 4, 2019Updated 6 years ago
- MNIST accelerator using binary qunatization on Xilinx pynq-z2☆14Sep 4, 2024Updated last year
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- High Granularity Quantizarion for Ultra-Fast Machine Learning Applications on FPGAs☆39Jul 23, 2025Updated 6 months ago
- ☆12Jul 20, 2022Updated 3 years ago
- A multicore microprocessor test harness for measuring interference☆14Apr 16, 2020Updated 5 years ago
- Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…☆19Jan 21, 2022Updated 4 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆374Jan 20, 2025Updated last year
- ☆91Apr 15, 2020Updated 5 years ago
- Successfully training approximations to full-rank matrices for efficiency in deep learning.☆17Jan 5, 2021Updated 5 years ago
- ☆15Jun 24, 2025Updated 7 months ago
- ☆16Apr 13, 2018Updated 7 years ago
- Train and deploy LUT-based neural networks on FPGAs☆106Jun 12, 2024Updated last year
- Static Block Floating Point Quantization for CNN☆37Jun 9, 2021Updated 4 years ago
- ☆72Feb 16, 2023Updated 2 years ago
- On the Effects of Quantisation on Model Uncertainty in Bayesian Neural Networks☆18Apr 8, 2024Updated last year
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Nov 7, 2019Updated 6 years ago
- ☆17Mar 2, 2021Updated 4 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆180Aug 16, 2025Updated 5 months ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Oct 7, 2025Updated 4 months ago