An LSTM template and a few examples using Vivado HLS
☆47May 4, 2024Updated 2 years ago
Alternatives and similar repositories for RNN_HLS
Users that are interested in RNN_HLS are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SAMO: Streaming Architecture Mapping Optimisation☆36Oct 4, 2023Updated 2 years ago
- ☆14Oct 26, 2023Updated 2 years ago
- ☆22Sep 27, 2022Updated 3 years ago
- ☆18Jan 22, 2025Updated last year
- DASS HLS Compiler☆31Oct 4, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Aug 22, 2021Updated 4 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆99Oct 2, 2021Updated 4 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆63Mar 17, 2022Updated 4 years ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆38Jul 22, 2020Updated 6 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆36Nov 7, 2024Updated last year
- ☆11Nov 5, 2019Updated 6 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆25Jun 28, 2019Updated 7 years ago
- ☆67May 6, 2020Updated 6 years ago
- FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks.☆28Aug 15, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆98Jan 29, 2026Updated 5 months ago
- An implementation of a BinaryConnect network for cifar10☆11Nov 4, 2019Updated 6 years ago
- ☆16Oct 29, 2021Updated 4 years ago
- Generate an FPGA design for a TWN☆11Nov 4, 2019Updated 6 years ago
- High-level synthesis (HLS) implementation of Sparse Matrix Vector Multiplication☆19Feb 17, 2022Updated 4 years ago
- MNIST accelerator using binary qunatization on Xilinx pynq-z2☆14Sep 4, 2024Updated last year
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆25Nov 8, 2024Updated last year
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago
- Personal Website☆11Jul 6, 2026Updated 2 weeks ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Fast inference of Boosted Decision Trees in FPGAs☆61Jul 6, 2026Updated 2 weeks ago
- Vitis HLS Library for FINN☆224May 27, 2026Updated last month
- Train and deploy LUT-based neural networks on FPGAs☆118Jun 12, 2024Updated 2 years ago
- ☆92Apr 15, 2020Updated 6 years ago
- implementing a Recurrent Neural Network with binarized weight format on FPGA☆22Sep 3, 2017Updated 8 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- On the Effects of Quantisation on Model Uncertainty in Bayesian Neural Networks☆18Apr 8, 2024Updated 2 years ago
- ☆11Dec 19, 2021Updated 4 years ago
- ☆16Mar 2, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Tutorial notebooks for hls4ml☆437Jul 13, 2026Updated last week
- A multicore microprocessor test harness for measuring interference☆14Apr 16, 2020Updated 6 years ago
- Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.☆28May 9, 2021Updated 5 years ago
- ☆34Nov 7, 2024Updated last year
- ☆12Jul 20, 2022Updated 4 years ago
- Static Block Floating Point Quantization for CNN☆38Jun 9, 2021Updated 5 years ago
- HLS code for a BNN accelerator☆17Sep 13, 2018Updated 7 years ago