HirokiNakahara / FPGA_lectureLinks
Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.
☆28Updated 4 years ago
Alternatives and similar repositories for FPGA_lecture
Users that are interested in FPGA_lecture are comparing it to the libraries listed below
Sorting:
- Binary Neural Network Framework for FPGA(Differentiable LUT)☆168Updated 4 months ago
- An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019☆18Updated 5 years ago
- NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network☆357Updated 2 years ago
- Polyphony is Python based High-Level Synthesis compiler.☆108Updated 11 months ago
- Board files to build Ultra 96 PYNQ image☆157Updated 3 months ago
- Sample scripts for FPGA-based AI Edge Contest 2019☆12Updated 5 years ago
- 10G Ethernet MAC implementation☆22Updated 5 years ago
- Train and deploy LUT-based neural networks on FPGAs☆109Updated last year
- PYNQ-Z1 board files for Vivado☆35Updated 3 years ago
- Repository of HW design and SW for Ultra96 board + MIPI board☆17Updated 6 years ago
- This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.☆107Updated 3 years ago
- HOG + SVM on FPGA☆27Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆74Updated 6 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆40Updated 4 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆108Updated 7 years ago
- Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2☆19Updated 5 years ago
- GUINNESS: A GUI-based binarized deep Neural NEtwork SyntheSizer toward an FPGA☆181Updated 6 years ago
- Original FPGA platform☆71Updated last week
- ☆28Updated 7 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- ☆64Updated 5 years ago
- Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…☆108Updated 3 years ago
- Basic Common Modules☆46Updated 2 weeks ago
- Caffe to VHDL☆68Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- Implementation VexRiscv on ultra96☆13Updated 3 years ago
- ☆30Updated 6 years ago
- PYNQ Composabe Overlays☆73Updated last year
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆31Updated last year