Alternatives and similar repositories for FPGA_lecture

Users that are interested in FPGA_lecture are comparing it to the libraries listed below

• rits-drsl / ZybotR2-96-fpt19
  An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019
  ☆17Updated 5 years ago
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆162Updated last month
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆155Updated 6 months ago
• HirokiNakahara / GUINNESS
  GUINNESS: A GUI-based binarized deep Neural NEtwork SyntheSizer toward an FPGA
  ☆181Updated 5 years ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆105Updated 5 months ago
• NNgen / nngen
  NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
  ☆354Updated last year
• fixstars / xg_mac
  10G Ethernet MAC implementation
  ☆21Updated 5 years ago
• cathalmccabe / pynq-z1_board_files
  PYNQ-Z1 board files for Vivado
  ☆34Updated 3 years ago
• PeterOgden / overlay_tutorial
  Premade bitstreams and block designs to complemented the PYNQ overlay tutorial
  ☆40Updated 3 years ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆97Updated last year
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆104Updated 2 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆105Updated 7 years ago
• lp6m / ImageDetectionHW2
  HOG + SVM on FPGA
  ☆26Updated 4 years ago
• Xilinx / Vitis-In-Depth-Tutorial
  ☆118Updated 4 years ago
• ikwzm / ZynqMP-FPGA-Linux
  FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)
  ☆130Updated last year
• ryuz / jelly
  Original FPGA platform
  ☆68Updated last week
• DreamIP / haddoc2
  Caffe to VHDL
  ☆67Updated 5 years ago
• HirokiNakahara / FPGA_AI_Edge_Contest_2019
  Sample scripts for FPGA-based AI Edge Contest 2019
  ☆11Updated 5 years ago
• template-hls / template-hls-float
  ☆29Updated 6 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆65Updated 5 years ago
• pezy-computing / pzbcm
  Basic Common Modules
  ☆41Updated last month
• awai54st / LUTNet
  ☆58Updated 5 years ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 5 years ago
• ikwzm / ZynqMP-FPGA-Ubuntu18.04-Ultra96
  Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2
  ☆19Updated 5 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆77Updated 9 years ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago
• lp6m / VexRiscv_Ultra96
  Implementation VexRiscv on ultra96
  ☆12Updated 3 years ago
• Avnet / vitis
  Vitis Repository for Avnet Designs
  ☆10Updated 3 months ago
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆38Updated 5 months ago
• AlexMontgomerie / fpgaconvnet-model
  Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
  ☆29Updated 8 months ago