Alternatives and similar repositories for FPGA_lecture

Users that are interested in FPGA_lecture are comparing it to the libraries listed below

• Xilinx / logicnets
  ☆94Updated last year
• fixstars / xg_mac
  10G Ethernet MAC implementation
  ☆21Updated 4 years ago
• ryuz / jelly
  Original FPGA platform
  ☆67Updated this week
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆161Updated 2 weeks ago
• PeterOgden / overlay_tutorial
  Premade bitstreams and block designs to complemented the PYNQ overlay tutorial
  ☆40Updated 3 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆63Updated 5 years ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆105Updated 4 months ago
• cathalmccabe / pynq-z1_board_files
  PYNQ-Z1 board files for Vivado
  ☆34Updated 3 years ago
• lp6m / ImageDetectionHW2
  HOG + SVM on FPGA
  ☆26Updated 4 years ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆104Updated 2 years ago
• ikwzm / ZynqMP-FPGA-Ubuntu18.04-Ultra96
  Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2
  ☆19Updated 5 years ago
• tukl-msd / LSTM-PYNQ
  ☆29Updated 7 years ago
• HirokiNakahara / GUINNESS
  GUINNESS: A GUI-based binarized deep Neural NEtwork SyntheSizer toward an FPGA
  ☆180Updated 5 years ago
• fixstars / ultra96_design
  Repository of HW design and SW for Ultra96 board + MIPI board
  ☆17Updated 6 years ago
• pezy-computing / pzbcm
  Basic Common Modules
  ☆39Updated last month
• HirokiNakahara / FPGA_AI_Edge_Contest_2019
  Sample scripts for FPGA-based AI Edge Contest 2019
  ☆11Updated 5 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• ikwzm / ZynqMP-FPGA-Linux
  FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)
  ☆130Updated last year
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆155Updated 6 months ago
• rits-drsl / ZybotR2-96-fpt19
  An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019
  ☆17Updated 5 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• kmanev / ZynqUSp-AXI-Speedtest
  ☆14Updated 5 years ago
• diningyo / dirv
  This is my first trial project for designing RISC-V in Chisel
  ☆17Updated last year
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆105Updated 7 years ago
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆38Updated 4 months ago
• DreamIP / haddoc2
  Caffe to VHDL
  ☆67Updated 5 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆76Updated 9 years ago
• Xilinx / kria-vitis-platforms
  Kria Vitis platforms and overlays
  ☆102Updated last month