sharc-lab / gnn-builderLinks
An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization
☆23Updated last year
Alternatives and similar repositories for gnn-builder
Users that are interested in gnn-builder are comparing it to the libraries listed below
Sorting:
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆11Updated 5 years ago
- An end-to-end GCN inference accelerator written in HLS☆18Updated 3 years ago
- NeuraChip Accelerator Simulator☆15Updated last year
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆18Updated last year
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- An HBM FPGA based SpMV Accelerator☆17Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- ☆16Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆21Updated 8 months ago
- ☆20Updated last year
- ACM TODAES Best Paper Award, 2022☆32Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 3 years ago
- ☆61Updated 8 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆72Updated 8 months ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆18Updated 3 years ago
- HW accelerator mapping optimization framework for in-memory computing☆25Updated 6 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆45Updated 3 weeks ago
- ☆10Updated 2 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- ☆32Updated last year
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆12Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆68Updated last week
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- Serpens is an HBM FPGA accelerator for SpMV☆22Updated last year
- Dataset for ML-guided Accelerator Design☆42Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 2 years ago