thesps / coniferLinks
Fast inference of Boosted Decision Trees in FPGAs
☆57Updated this week
Alternatives and similar repositories for conifer
Users that are interested in conifer are comparing it to the libraries listed below
Sorting:
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- ☆35Updated 6 years ago
- An LSTM template and a few examples using Vivado HLS☆47Updated last year
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆204Updated 4 years ago
- ☆65Updated 5 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆104Updated 2 weeks ago
- Models and examples built with hls4ml☆12Updated 5 years ago
- NeuraLUT-Assemble☆47Updated 5 months ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 4 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 6 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated 2 years ago
- Vitis HLS Library for FINN☆213Updated 3 weeks ago
- Open-Source HLS Examples for Microchip FPGAs☆49Updated last week
- ☆30Updated 6 years ago
- High Granularity Quantizarion for Ultra-Fast Machine Learning Applications on FPGAs☆39Updated 6 months ago
- PYNQ Bootcamp 2019-2024 teaching materials.☆52Updated last year
- PYNQ Composabe Overlays☆74Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Updated last year
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆55Updated last year
- ☆22Updated 3 years ago
- PyTorch model to RTL flow for low latency inference☆131Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆128Updated 3 years ago
- ☆109Updated 6 years ago
- Dataflow QNN inference accelerator examples on FPGAs☆241Updated 5 months ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆33Updated last year
- Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…☆19Updated 4 years ago