Alternatives and similar repositories for conifer:

Users that are interested in conifer are comparing it to the libraries listed below

• Xilinx / logicnets
  ☆87Updated 9 months ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆191Updated last week
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• awai54st / LUTNet
  ☆57Updated 4 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆75Updated last month
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆29Updated 4 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆32Updated last year
• calad0i / HGQ
  High Granularity Quantizarion for Ultra-Fast Machine Learning Applications on FPGAs
  ☆25Updated 2 months ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆57Updated 3 years ago
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆122Updated 2 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆70Updated 9 months ago
• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆209Updated this week
• Xilinx / DSP-PYNQ
  A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+
  ☆39Updated 2 years ago
• twaclaw / matmult
  A floating-point matrix multiplication implemented in hardware
  ☆31Updated 4 years ago
• rapidstream-org / rapidstream-tapa
  RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆165Updated this week
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆44Updated 10 months ago
• Xilinx / xup_compute_acceleration
  Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
  ☆46Updated 8 months ago
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆199Updated 3 years ago
• FPGA4HEP / course_material
  ☆35Updated 5 years ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆121Updated 2 years ago
• Xilinx / finn-base
  Open Source Compiler Framework using ONNX as Frontend and IR
  ☆29Updated 2 years ago
• IMPETUS-UdeS / rule4ml
  Resource Utilization and Latency Estimation for ML on FPGA.
  ☆10Updated 2 weeks ago
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆126Updated last year
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• maltanar / qnn-inference-examples
  Jupyter notebook examples on image classification with quantized neural networks
  ☆70Updated 4 years ago
• AlexMontgomerie / fpgaconvnet-model
  Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
  ☆29Updated 4 months ago
• lana555 / dynamatic
  ☆86Updated last year
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆101Updated 2 years ago
• Xilinx / PYNQ-ZU
  PYNQ-ZU, XUP UltraScale+ MPSoC academic board
  ☆22Updated 6 months ago