Alternatives and similar repositories for conifer

Users that are interested in conifer are comparing it to the libraries listed below

• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• FPGA4HEP / course_material
  ☆35Updated 5 years ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• Xilinx / logicnets
  ☆94Updated 11 months ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆45Updated last year
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆33Updated last year
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆58Updated 3 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆79Updated 2 weeks ago
• MartaAndronic / NeuraLUT
  NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions
  ☆32Updated 2 months ago
• fastmachinelearning / models
  Models and examples built with hls4ml
  ☆12Updated 5 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆198Updated this week
• twaclaw / matmult
  A floating-point matrix multiplication implemented in hardware
  ☆31Updated 4 years ago
• AlexMontgomerie / fpgaconvnet-model
  Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
  ☆29Updated 7 months ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆72Updated 11 months ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆126Updated 2 years ago
• UofT-HPRC / galapagos
  ☆14Updated 3 months ago
• Xilinx / xup_compute_acceleration
  Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
  ☆47Updated 10 months ago
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆126Updated last year
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆51Updated 5 years ago
• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆217Updated 2 months ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆47Updated 4 years ago
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆122Updated 2 years ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆23Updated 5 months ago
• template-hls / template-hls-float
  ☆29Updated 6 years ago
• Xilinx / finn-base
  Open Source Compiler Framework using ONNX as Frontend and IR
  ☆30Updated 2 years ago
• icgrp / prflow_nested_dfx
  Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)
  ☆14Updated last year
• maltanar / qnn-inference-examples
  Jupyter notebook examples on image classification with quantized neural networks
  ☆69Updated 5 years ago