thesps / conifer
Fast inference of Boosted Decision Trees in FPGAs
☆53Updated last month
Alternatives and similar repositories for conifer
Users that are interested in conifer are comparing it to the libraries listed below
Sorting:
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- ☆92Updated 11 months ago
- Vitis HLS Library for FINN☆193Updated this week
- SAMO: Streaming Architecture Mapping Optimisation☆32Updated last year
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆77Updated this week
- ☆57Updated 5 years ago
- PYNQ Composabe Overlays☆71Updated 10 months ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆47Updated 9 months ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆58Updated 3 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- Dataflow QNN inference accelerator examples on FPGAs☆213Updated last month
- High Granularity Quantizarion for Ultra-Fast Machine Learning Applications on FPGAs☆27Updated last month
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆34Updated 5 years ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆39Updated 2 years ago
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆29Updated 6 months ago
- A course based on FINN with hands on Lectures, Examples and Labs to go from 0 to a full custom Quantized Neural Network running on your v…☆20Updated 6 months ago
- Library of approximate arithmetic circuits☆53Updated 2 years ago
- ☆106Updated 5 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆44Updated 4 years ago
- This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.☆102Updated 2 years ago
- Open Source Compiler Framework using ONNX as Frontend and IR☆30Updated 2 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- FOS - FPGA Operating System☆66Updated 4 years ago
- Models and examples built with hls4ml☆12Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 7 years ago
- Verilog Implementation of 32-bit Floating Point Adder☆40Updated 5 years ago
- Resource Utilization and Latency Estimation for ML on FPGA.☆10Updated 2 months ago
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago