Stuart0l / BNNLinks
HLS code for a BNN accelerator
☆17Updated 7 years ago
Alternatives and similar repositories for BNN
Users that are interested in BNN are comparing it to the libraries listed below
Sorting:
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆52Updated 7 years ago
- A DNN Accelerator implemented with RTL.☆68Updated 11 months ago
- hls code zynq 7020 pynq z2 CNN☆88Updated 6 years ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆37Updated 5 years ago
- The second place winner for DAC-SDC 2020☆98Updated 3 years ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆72Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- 中文:☆106Updated 6 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆115Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆196Updated 7 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆71Updated 6 years ago
- FPGA☆159Updated last year
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆27Updated 4 years ago
- Codes to implement MobileNet V2 in a FPGA☆28Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆191Updated last year
- The CNN based on the Xilinx Vivado HLS☆37Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆113Updated 8 years ago
- Some attempts to build CNN on PYNQ.☆25Updated 6 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆48Updated 5 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆13Updated last year
- ☆56Updated 2 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆103Updated last year
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆40Updated 5 years ago
- ☆98Updated 5 years ago
- FPGA/AES/LeNet/VGG16☆109Updated 7 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆24Updated 6 years ago
- ☆123Updated 5 years ago