Stuart0l / BNNLinks
HLS code for a BNN accelerator
☆16Updated 6 years ago
Alternatives and similar repositories for BNN
Users that are interested in BNN are comparing it to the libraries listed below
Sorting:
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- A DNN Accelerator implemented with RTL.☆67Updated 7 months ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- 中文:☆101Updated 5 years ago
- hls code zynq 7020 pynq z2 CNN☆83Updated 6 years ago
- Codes to implement MobileNet V2 in a FPGA☆27Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆190Updated 7 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆43Updated 6 years ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆40Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- FPGA☆158Updated last year
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆37Updated 5 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆186Updated last year
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆72Updated 5 years ago
- ☆47Updated 7 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- FPGA Accelerator for CNN using Vivado HLS☆319Updated 3 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆70Updated 6 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆157Updated 2 years ago
- FPGA/AES/LeNet/VGG16☆104Updated 6 years ago
- 【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码☆78Updated 3 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆95Updated last year
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆183Updated last year
- ☆90Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆220Updated 2 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆24Updated 3 years ago
- Some attempts to build CNN on PYNQ.☆24Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago