Lenet for MNIST handwritten digit recognition using Vivado hls tool
☆38Jul 22, 2020Updated 6 years ago
Alternatives and similar repositories for mnist_hls
Users that are interested in mnist_hls are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The CNN based on the Xilinx Vivado HLS☆37Oct 27, 2021Updated 4 years ago
- HLS code for a BNN accelerator☆17Sep 13, 2018Updated 7 years ago
- An LSTM template and a few examples using Vivado HLS☆47May 4, 2024Updated 2 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53May 29, 2018Updated 8 years ago
- FPGA and GPU acceleration of LeNet5☆36Jul 9, 2019Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- MTCNN with convolution reprogramed in c☆14Jul 25, 2019Updated 7 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆74Jun 11, 2019Updated 7 years ago
- FPGA Accelerator for CNN using Vivado HLS☆340Oct 25, 2021Updated 4 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Mar 5, 2018Updated 8 years ago
- A demo for accelerating sobel in xilinx's fpga pynq☆19Jan 31, 2023Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆54Jul 18, 2021Updated 5 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆36Nov 7, 2024Updated last year
- An Accelerator for Convolution layer designed with Vivado HLS.☆10Dec 4, 2020Updated 5 years ago
- Zynq PR Management☆13Apr 20, 2016Updated 10 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Huffman encoding core (Vivado HLS Project)☆12Oct 15, 2019Updated 6 years ago
- MNIST accelerator using binary qunatization on Xilinx pynq-z2☆14Sep 4, 2024Updated 2 years ago
- Some attempts to build CNN on PYNQ.☆25Jun 28, 2019Updated 7 years ago
- Convolutional Neural Net written for implementation on an FPGA☆21Jun 26, 2017Updated 9 years ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 7 years ago
- Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs☆21Jun 4, 2020Updated 6 years ago
- A single instruction set processor architecture☆19Jul 31, 2017Updated 9 years ago
- c++ version of ViT☆13Nov 13, 2022Updated 3 years ago
- ☆24Sep 23, 2015Updated 10 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- a student trainning project for HLS and transformer☆11Oct 19, 2022Updated 3 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆116Jun 24, 2017Updated 9 years ago
- FPGA implementation of a handwritten digit recognition system based on k-nearest-neighbors (k-NN) classifier algorithm.☆21Apr 3, 2018Updated 8 years ago
- ☆14Oct 24, 2022Updated 3 years ago
- ☆11Sep 3, 2022Updated 4 years ago
- XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA☆22Mar 7, 2024Updated 2 years ago
- An FPGA implementation of a digital storage oscilloscope.☆28Apr 20, 2017Updated 9 years ago
- A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard☆924Jul 29, 2024Updated 2 years ago
- Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis☆17Dec 9, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- An implementation of a BinaryConnect network for cifar10☆11Nov 4, 2019Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆88Sep 23, 2020Updated 5 years ago
- Generate an FPGA design for a TWN☆11Nov 4, 2019Updated 6 years ago
- OpenReroc (Open source Reconfigurable robot component)☆10Oct 17, 2016Updated 9 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆24Jul 29, 2022Updated 4 years ago
- ☆14Oct 26, 2023Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆17Jun 23, 2020Updated 6 years ago