FloyedShen / mnist_hlsLinks
Lenet for MNIST handwritten digit recognition using Vivado hls tool
☆37Updated 5 years ago
Alternatives and similar repositories for mnist_hls
Users that are interested in mnist_hls are comparing it to the libraries listed below
Sorting:
- hls code zynq 7020 pynq z2 CNN☆86Updated 6 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆188Updated last year
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆169Updated 2 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 4 years ago
- An LeNet RTL implement onto FPGA☆50Updated 7 years ago
- 中文:☆104Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆88Updated 5 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆102Updated last year
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆71Updated 6 years ago
- A DNN Accelerator implemented with RTL.☆67Updated 9 months ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆47Updated 5 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- FPGA☆160Updated last year
- FPGA/AES/LeNet/VGG16☆108Updated 7 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆160Updated 4 years ago
- Convolutional Neural Network RTL-level Design☆72Updated 4 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆230Updated 2 years ago
- PYNQ学习资料☆171Updated 5 years ago
- ☆48Updated 7 years ago
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆43Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆66Updated 7 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆168Updated last year
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆83Updated 4 years ago
- Nuclei E203 with yolo accelerator based on xc7k325☆18Updated last year
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆74Updated 7 months ago
- CNN accelerator implemented with Spinal HDL☆154Updated last year
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆242Updated 6 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆202Updated 2 weeks ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆40Updated 5 years ago