Xilinx / brevitas-radioml-challenge-21Links
☆16Updated 4 years ago
Alternatives and similar repositories for brevitas-radioml-challenge-21
Users that are interested in brevitas-radioml-challenge-21 are comparing it to the libraries listed below
Sorting:
- Classify modulation of signals☆15Updated 5 years ago
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- Generate an FPGA design for a TWN☆10Updated 6 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- 🧠 Benchmark facility to train networks on different datasets for PyTorch/Brevitas☆26Updated 2 years ago
- ☆60Updated 5 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated 2 years ago
- ☆20Updated 3 years ago
- Fast inference of Boosted Decision Trees in FPGAs☆57Updated last week
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆40Updated 3 years ago
- Jupyter notebook examples on image classification with quantized neural networks☆70Updated 5 years ago
- Models and examples built with hls4ml☆12Updated 5 years ago
- ☆109Updated 6 years ago
- PYNQ-ZU, AUP UltraScale+ MPSoC academic board☆27Updated 3 weeks ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- ☆32Updated 11 months ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆72Updated 5 years ago
- FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks.☆26Updated 2 years ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆54Updated last year
- Train and deploy LUT-based neural networks on FPGAs☆100Updated last year
- ☆10Updated last year
- Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…☆17Updated 3 years ago
- ☆35Updated 6 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆21Updated last year
- UCSD CSE 237D Spring '20 Course Project☆18Updated 2 years ago
- NeuraLUT-Assemble☆43Updated 2 months ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆32Updated 6 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆15Updated 8 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- High Granularity Quantizarion for Ultra-Fast Machine Learning Applications on FPGAs☆36Updated 3 months ago