Xilinx / brevitas-radioml-challenge-21

Related projects ⓘ

Alternatives and complementary repositories for brevitas-radioml-challenge-21

• louisinhit / CNN-for-modulation-recognition-based-on-FPGA
  ☆18Updated 2 years ago
• da-steve101 / radio_modulation
  Classify modulation of signals
  ☆15Updated 4 years ago
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆42Updated 6 months ago
• strath-sdr / rfsoc_notebooks
  A collection of RFSoC introductory notebooks for PYNQ.
  ☆19Updated 3 years ago
• enyac-group / MaxEVA
  MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)
  ☆15Updated 6 months ago
• Xilinx / RFNoC-HLS-NeuralNet
  ☆104Updated 5 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆51Updated 2 years ago
• AlexMontgomerie / fpgaconvnet-model
  Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
  ☆27Updated this week
• 0BAB1 / python_to_fpga_course
  A course based on FINN with hands on Lectures, Examples and Labs to go from 0 to a full custom Quantized Neural Network running on your v…
  ☆14Updated 2 weeks ago
• da-steve101 / twn_generator
  Generate an FPGA design for a TWN
  ☆9Updated 5 years ago
• AlexMontgomerie / fpgaconvnet-hls
  ☆24Updated this week
• arun1993 / FPGA-Wireless-communication-blocks
  Implementation of Wireless communication blocks such as FFT, OFDM receiver, Polar code decoder in a FPGA using Vivado HLS
  ☆21Updated 3 years ago
• jonathan93sh / CNNA
  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
  ☆21Updated 3 years ago
• nikulshr / resnet_fpga
  UCSD CSE 237D Spring '20 Course Project
  ☆14Updated last year
• KastnerRG / Read_the_docs
  Projects and Labs for the Parallel Programming for FPGAs book
  ☆13Updated last week
• os-hxfan / BayesNN_FPGA
  FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks.
  ☆20Updated last year
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆39Updated 9 months ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆32Updated last year
• JennySmith888 / 100GBE-PYNQ
  ☆18Updated 3 years ago
• linxiaobo110 / rps_u96
  ☆12Updated 4 years ago
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 2 years ago
• sainathiyer / Hardware-Implementation-of-Polar-Code-for-5G-Application-on-FPGA
  Polar codes are error correction codes developed by Erdal Arikan which achieves channel capacity and its reduced complexity makes it more…
  ☆15Updated 3 years ago
• asadalam / FINN_MatrixVector_RTL
  Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…
  ☆15Updated 2 years ago
• Lcrypto / FEC-Archive-Verilog
  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…
  ☆53Updated last year
• lab-emi / OpenDPD
  OpenDPD is an end-to-end learning framework built in PyTorch for power amplifier (PA) modeling and digital pre-distortion (DPD). You are …
  ☆43Updated 2 weeks ago
• manoharvhr / PYNQ-Torch
  PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform
  ☆66Updated 4 years ago
• Xilinx / DSP-PYNQ
  A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+
  ☆37Updated 2 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆24Updated 4 years ago
• UCLA-VAST / CLINK
  Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.
  ☆17Updated 5 years ago
• strath-sdr / dsp_notebooks
  A collection of Digital Signal Processing notebooks with a wireless communications theme.
  ☆103Updated last year