Alternatives and similar repositories for fpgaconvnet-model

Users that are interested in fpgaconvnet-model are comparing it to the libraries listed below

• AlexMontgomerie / fpgaconvnet-hls
  ☆30Updated 6 months ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆39Updated 8 months ago
• MartaAndronic / NeuraLUT
  NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions
  ☆32Updated 2 months ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆45Updated last year
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆45Updated 2 years ago
• ptoupas / amd-open-hardware-23
  This repository provides an FPGA-based solution for executing object detection, focusing specifically on the popular YOLOv5 model archite…
  ☆42Updated last year
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆72Updated 11 months ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• Xilinx / logicnets
  ☆94Updated 11 months ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆52Updated 3 years ago
• Kareem-Emad / DCNN-Accelerator
  Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.
  ☆12Updated 6 years ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 4 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆58Updated 3 years ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago
• awai54st / Logic-Shrinkage
  ☆23Updated 2 years ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆56Updated 4 months ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆79Updated 2 weeks ago
• lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
  This project implements a convolution kernel based on vivado HLS on zcu104
  ☆37Updated 5 years ago
• jonathan93sh / CNNA
  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
  ☆24Updated 3 years ago
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆53Updated last year
• abdelfattah-lab / BRAMAC
  ☆10Updated 6 months ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆33Updated last year
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆31Updated 2 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 4 years ago
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆14Updated 4 years ago
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆36Updated 2 weeks ago