AlexMontgomerie / fpgaconvnet-modelLinks
Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
☆31Updated last year
Alternatives and similar repositories for fpgaconvnet-model
Users that are interested in fpgaconvnet-model are comparing it to the libraries listed below
Sorting:
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 4 years ago
- A collection of tutorials for the fpgaConvNet framework.☆47Updated last year
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- ☆32Updated last year
- An LSTM template and a few examples using Vivado HLS☆46Updated last year
- ☆72Updated 2 years ago
- NeuraLUT-Assemble☆46Updated 4 months ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆55Updated last year
- This repository provides an FPGA-based solution for executing object detection, focusing specifically on the popular YOLOv5 model archite…☆48Updated 2 years ago
- Vitis HLS Library for FINN☆213Updated this week
- ☆64Updated 5 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆102Updated this week
- HLS implemented systolic array structure☆41Updated 8 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆95Updated 4 years ago
- ☆72Updated 7 years ago
- Verilog implementation of Softmax function☆77Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆61Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 10 months ago
- Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…☆19Updated 3 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- ☆39Updated 3 weeks ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆116Updated 11 months ago
- AMD University Program HLS tutorial☆123Updated last year
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆28Updated 4 years ago