Alternatives and similar repositories for Logic-Shrinkage:

Users that are interested in Logic-Shrinkage are comparing it to the libraries listed below

• MartaAndronic / NeuraLUT
  NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions
  ☆29Updated last month
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• awai54st / LUTNet
  ☆57Updated 5 years ago
• template-hls / template-hls-float
  ☆29Updated 6 years ago
• Xilinx / logicnets
  ☆91Updated 10 months ago
• enyac-group / MaxEVA
  MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)
  ☆20Updated last year
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• fffasttime / AnyPackingNet
  ☆26Updated last month
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• ebby-s / MX-for-FPGA
  Implementation of Microscaling data formats in SystemVerilog.
  ☆17Updated 8 months ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆40Updated 7 months ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆76Updated 3 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆52Updated 2 weeks ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆51Updated last week
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆34Updated last week
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆32Updated last year
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 4 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆45Updated 2 months ago
• arc-research-lab / AIM
  AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…
  ☆22Updated last month
• lite-david / comet
  RISC-V ISA based 32-bit processor written in HLS
  ☆17Updated 5 years ago
• priyanka-raina / dnn-accelerator
  ☆13Updated 4 years ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆44Updated last month
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆79Updated 9 months ago
• gem5-X / TiC-SAT
  ☆15Updated 10 months ago
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆51Updated last year
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago