andrewboutros / rad-flowLinks
The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration devices (RADs). These devices incorporate conventional FPGA fabrics, several coarse-grained domain-specialized accelerator blocks, and high-performance networks-on-chip for system-level communication.
☆38Updated 2 months ago
Alternatives and similar repositories for rad-flow
Users that are interested in rad-flow are comparing it to the libraries listed below
Sorting:
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆174Updated last month
- A fast, accurate trace-based simulator for High-Level Synthesis.☆69Updated 6 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆138Updated 3 months ago
- An integrated CGRA design framework☆91Updated 6 months ago
- ☆49Updated 3 months ago
- An Open-Source Tool for CGRA Accelerators☆74Updated 3 weeks ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆125Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆84Updated last year
- ☆31Updated 11 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆160Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated 3 months ago
- An Open-Source Tool for CGRA Accelerators☆24Updated 3 weeks ago
- ☆72Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆63Updated 11 months ago
- RTL implementation of Flex-DPE.☆112Updated 5 years ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆47Updated 2 months ago
- ☆87Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆157Updated this week
- ☆15Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆64Updated 2 weeks ago
- ☆59Updated 6 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated last month
- A list of our chiplet simulaters☆41Updated 3 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆66Updated last week
- An Open-Hardware CGRA for accelerated computation on the edge.☆35Updated last year
- ☆13Updated 2 years ago