The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration devices (RADs). These devices incorporate conventional FPGA fabrics, several coarse-grained domain-specialized accelerator blocks, and high-performance networks-on-chip for system-level communication.
☆38Jul 22, 2025Updated 7 months ago
Alternatives and similar repositories for rad-flow
Users that are interested in rad-flow are comparing it to the libraries listed below
Sorting:
- ☆10Nov 13, 2025Updated 3 months ago
- ☆46Sep 13, 2024Updated last year
- ☆17Nov 18, 2025Updated 3 months ago
- ☆12Apr 15, 2025Updated 10 months ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆25May 18, 2025Updated 9 months ago
- NeuraChip Accelerator Simulator☆16Apr 26, 2024Updated last year
- ☆14Feb 14, 2022Updated 4 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆73Sep 29, 2025Updated 5 months ago
- ☆14Feb 28, 2023Updated 3 years ago
- ☆17Feb 3, 2023Updated 3 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆21Jan 12, 2024Updated 2 years ago
- Parsing library for BLIF netlists☆19Nov 1, 2024Updated last year
- RTL implementation of Flex-DPE.☆115Feb 22, 2020Updated 6 years ago
- The OpenPiton Platform☆17Aug 14, 2024Updated last year
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆27Nov 1, 2025Updated 4 months ago
- Quick & Flexible Rack-Scale Computer Architecture Simulator☆53Feb 24, 2026Updated last week
- ordspecsim: The Swarm architecture simulator☆24Feb 15, 2023Updated 3 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last week
- GL0AM GPU Accelerated Gate Level Logic Simulator☆30Feb 11, 2026Updated 3 weeks ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Jun 18, 2020Updated 5 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆164Updated this week
- A fast, accurate trace-based simulator for High-Level Synthesis.☆74Dec 19, 2025Updated 2 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆185Jan 23, 2026Updated last month
- AutoSA: Polyhedral-Based Systolic Array Compiler☆239Dec 8, 2022Updated 3 years ago
- ☆24May 6, 2023Updated 2 years ago
- This repository describes I/O traces of Google storage servers and disks synthesized by Thesios. Thesios synthesizes representative I/O t…☆25Apr 29, 2024Updated last year
- ☆62Updated this week
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆77Feb 26, 2026Updated last week
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆116Apr 9, 2025Updated 10 months ago
- The first version of TritonPart☆31Jan 2, 2024Updated 2 years ago
- Qingnang Smart Diagnosis is an end-to-end AI healthcare framework with field-proven application capabilities, designed to provide efficie…☆15Nov 11, 2025Updated 3 months ago
- AI companion platform with original layered memory algorithm, multi-AI collaboration engine & IDE interface. SillyTavern compatible. | 原创…☆35Feb 28, 2026Updated last week
- Implementation of NIPS2023: Unleashing the Full Potential of Product Quantization for Large-Scale Image Retrieva☆11Nov 12, 2024Updated last year
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆32Nov 13, 2023Updated 2 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆404Updated this week
- ☆72Feb 16, 2023Updated 3 years ago
- A reference implementation of the Mind Mappings Framework.☆30Dec 2, 2021Updated 4 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆35Jun 3, 2025Updated 9 months ago
- A benchmark suite to study the performance characteristics of genomics applications☆32Oct 21, 2024Updated last year