andrewboutros / rad-flowLinks
The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration devices (RADs). These devices incorporate conventional FPGA fabrics, several coarse-grained domain-specialized accelerator blocks, and high-performance networks-on-chip for system-level communication.
☆38Updated last month
Alternatives and similar repositories for rad-flow
Users that are interested in rad-flow are comparing it to the libraries listed below
Sorting:
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆136Updated 3 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 3 years ago
- ☆31Updated 10 months ago
- An integrated CGRA design framework☆90Updated 5 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- An Open-Source Tool for CGRA Accelerators☆72Updated this week
- A fast, accurate trace-based simulator for High-Level Synthesis.☆68Updated 5 months ago
- ☆72Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆174Updated last month
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆124Updated 2 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆158Updated 2 years ago
- ☆24Updated 4 years ago
- ☆63Updated 4 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated 2 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- ☆58Updated 5 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆84Updated last year
- ☆49Updated 2 months ago
- ☆87Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 3 weeks ago
- ☆17Updated 4 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆155Updated this week
- ☆44Updated last year
- gem5 repository to study chiplet-based systems☆81Updated 6 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆63Updated 3 weeks ago
- RTL implementation of Flex-DPE.☆110Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆47Updated 6 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆69Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆61Updated 11 months ago