andrewboutros / rad-flow
The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration devices (RADs). These devices incorporate conventional FPGA fabrics, several coarse-grained domain-specialized accelerator blocks, and high-performance networks-on-chip for system-level communication.
☆34Updated last month
Alternatives and similar repositories for rad-flow:
Users that are interested in rad-flow are comparing it to the libraries listed below
- ☆44Updated last month
- An Open-Source Tool for CGRA Accelerators☆64Updated 2 weeks ago
- ☆71Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆21Updated last year
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆34Updated last week
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated last week
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆24Updated 7 months ago
- ☆42Updated 7 months ago
- Dataset for ML-guided Accelerator Design☆36Updated 5 months ago
- ☆50Updated last month
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 7 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- ☆86Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆58Updated 6 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆76Updated 3 years ago
- An integrated CGRA design framework☆88Updated last month
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆71Updated 6 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- CGRA framework with vectorization support.☆29Updated 2 weeks ago
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆14Updated 6 months ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆14Updated last year
- eyeriss-chisel3☆40Updated 3 years ago
- ☆59Updated this week
- Ratatoskr NoC Simulator☆24Updated 4 years ago
- A hardware synthesis framework with multi-level paradigm☆38Updated 3 months ago
- Project repo for the POSH on-chip network generator☆45Updated last month
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- CATCH 1.0, Initial full release of CATCH cost model.☆14Updated 2 months ago
- DASS HLS Compiler☆29Updated last year