andrewboutros / rad-flow
The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration devices (RADs). These devices incorporate conventional FPGA fabrics, several coarse-grained domain-specialized accelerator blocks, and high-performance networks-on-chip for system-level communication.
☆33Updated last week
Alternatives and similar repositories for rad-flow:
Users that are interested in rad-flow are comparing it to the libraries listed below
- Dataset for ML-guided Accelerator Design☆36Updated 4 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆34Updated this week
- ☆86Updated last year
- ☆71Updated 2 years ago
- ☆48Updated 2 weeks ago
- ☆41Updated 7 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆44Updated 2 weeks ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 6 months ago
- ☆59Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆73Updated 3 years ago
- An integrated CGRA design framework☆87Updated 3 weeks ago
- ☆42Updated 3 weeks ago
- An Open-Source Tool for CGRA Accelerators☆61Updated 3 months ago
- ☆23Updated 4 years ago
- ☆26Updated 5 months ago
- DASS HLS Compiler☆29Updated last year
- ☆57Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆70Updated 5 years ago
- CGRA framework with vectorization support.☆29Updated this week
- ☆15Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆13Updated last year
- Ratatoskr NoC Simulator☆24Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- ☆10Updated 2 years ago
- A list of our chiplet simulaters☆32Updated last week
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆13Updated 6 months ago