Alternatives and similar repositories for BRAMAC

Users that are interested in BRAMAC are comparing it to the libraries listed below

• fffasttime / AnyPackingNet
  ☆32Updated 10 months ago
• eda-lab / CNNAF-CNN-Accelerator
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆11Updated 4 years ago
• lukasc-ch / ExtendedBitPlaneCompression
  Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…
  ☆19Updated 6 years ago
• nimish15shah / DAG_Processor
  A DAG processor and compiler for a tree-based spatial datapath.
  ☆15Updated 3 years ago
• mustard-seed / SparseDNNAccelerator
  Sparse CNN Accelerator targeting Intel FPGA
  ☆12Updated 4 years ago
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆55Updated 2 years ago
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆97Updated 4 years ago
• sharc-lab / DGNN-Booster
  ☆16Updated 2 years ago
• ChrisZonghaoLi / cnn_conv_accelerator
  A Fix-pointed Rudimentary CNN Convolution Accelerator
  ☆16Updated 5 years ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago
• hqjenny / CoDeNet
  ☆19Updated 4 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆49Updated last year
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago
• SivannaKing / SEU-ASIC-IOT-ECGAI
  Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators
  ☆16Updated 2 years ago
• gicLAB / SECDA
  ☆26Updated 3 years ago
• haroonrl / DNN_HLS_Accelerator
  This repository contains source code for CNN layers of ALexNet using Xilinx HLS Vivado.
  ☆10Updated 3 years ago
• enyac-group / MaxEVA
  MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)
  ☆21Updated last year
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• awai54st / Logic-Shrinkage
  ☆22Updated 3 years ago
• racosa / cnn-accelerator
  A Convolutional Neural Network (CNN) hardware accelerator for image recognition
  ☆14Updated 6 years ago
• awai54st / LUTNet
  ☆65Updated 5 years ago
• nimish15shah / DPU_DAG_Processing_Unit
  RTL code for the DPU chip designed for irregular graphs
  ☆13Updated 3 years ago
• albertomarchisio / SwiftTron
  ☆46Updated 2 years ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆34Updated 2 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆50Updated 11 months ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆21Updated 3 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆92Updated last year
• AiArtisan / dac_sdc_2022_champion
  ☆21Updated 3 years ago
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆47Updated last year