fbrosser / DSP48E1-FPLinks
Project aimed at implementing floating point operators using the DSP48E1 slice.
☆29Updated 12 years ago
Alternatives and similar repositories for DSP48E1-FP
Users that are interested in DSP48E1-FP are comparing it to the libraries listed below
Sorting:
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 11 months ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆30Updated 6 months ago
- ☆36Updated 2 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 4 months ago
- An automatic clock gating utility☆49Updated 2 months ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- ☆30Updated 2 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated 11 months ago
- Docker Development Environment for SpinalHDL☆20Updated 10 months ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆41Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated 2 weeks ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- ☆33Updated 2 years ago
- ☆26Updated 4 years ago
- LIS Network-on-Chip Implementation☆30Updated 8 years ago
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- ☆59Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆62Updated 7 months ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- sram/rram/mram.. compiler☆35Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last year