Project aimed at implementing floating point operators using the DSP48E1 slice.
☆30Mar 29, 2013Updated 13 years ago
Alternatives and similar repositories for DSP48E1-FP
Users that are interested in DSP48E1-FP are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 10 months ago
- XC2064 bitstream documentation☆19Sep 24, 2018Updated 8 years ago
- PCIe analyzer experiments☆69May 21, 2020Updated 6 years ago
- Firmware and Gateware for the DiVA platform.☆14Sep 8, 2025Updated last year
- FPGA synthesis tool powered by equality saturation and program synthesis.☆15Jan 9, 2026Updated 9 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- lightweight open HLS for FPGA rapid prototyping☆20Mar 22, 2018Updated 8 years ago
- PCIe stack written in Amaranth.☆18Apr 27, 2026Updated 5 months ago
- iDEA FPGA Soft Processor☆17Jun 9, 2016Updated 10 years ago
- SPI flash MITM and emulation (QSPI is a WIP)☆22Jan 27, 2022Updated 4 years ago
- photonSDI - an open source SDI core☆11May 26, 2021Updated 5 years ago
- PCIe to .1 inch header breakout☆11Sep 14, 2020Updated 6 years ago
- Full Speed USB DFU interface for FPGA and ASIC designs☆21Mar 10, 2024Updated 2 years ago
- Project Trellis database☆16Updated this week
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated 8 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆19Dec 5, 2022Updated 3 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆21Sep 3, 2019Updated 7 years ago
- Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.☆19Feb 9, 2022Updated 4 years ago
- Stencil with Optimized Dataflow Architecture☆12Feb 27, 2024Updated 2 years ago
- A computer (FPGA SoC) based on the MRISC32-A1 CPU☆53Sep 2, 2023Updated 3 years ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 6 years ago
- Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA☆213Feb 28, 2019Updated 7 years ago
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆30Jan 21, 2025Updated last year
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Next-Generation FPGA Place-and-Route☆10Aug 1, 2018Updated 8 years ago
- 4k Mixed Reality headset☆40Oct 7, 2017Updated 9 years ago
- Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research☆17Jan 21, 2024Updated 2 years ago
- Generate bitstream from FPGA assembly.☆30Updated this week
- A bit-serial CPU☆20Sep 29, 2019Updated 7 years ago
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆27Apr 24, 2019Updated 7 years ago
- AXI support for Migen/MiSoC☆28Oct 1, 2026Updated last week
- ice40 UltraPlus demos☆16Oct 4, 2019Updated 7 years ago
- gateware for the main fpga, including a hispi decoder and image processing☆13Sep 27, 2018Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Utilities for working with a Wishbone bus in an embedded device☆48Aug 29, 2025Updated last year
- The Verilog source code for DRUM approximate multiplier.☆32May 4, 2023Updated 3 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- Tool for graphically viewing FPGA bitstream files and their connection to FASM features.☆19Apr 6, 2022Updated 4 years ago
- Smol 2-stage RISC-V processor in nMigen☆27May 6, 2021Updated 5 years ago
- ☆34Oct 2, 2023Updated 3 years ago
- Library of FPGA architectures☆33Sep 28, 2026Updated 2 weeks ago