zslwyuan / Hi-DMMLinks
Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)
☆25Updated 6 years ago
Alternatives and similar repositories for Hi-DMM
Users that are interested in Hi-DMM are comparing it to the libraries listed below
Sorting:
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆61Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆52Updated 8 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- Documentation for the entire CGRAFlow☆19Updated 4 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 8 years ago
- ☆29Updated 8 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆37Updated 4 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆49Updated 3 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 4 months ago
- The Chronos FPGA Framework to accelerate ordered applications☆22Updated 5 years ago
- An infrastructure for integrated EDA☆41Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆126Updated 2 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- ☆27Updated 5 years ago
- CGRA Compilation Framework☆88Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆19Updated 6 years ago
- ☆98Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆18Updated last week
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- ☆24Updated 4 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago