zslwyuan / Hi-DMM
Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)
☆25Updated 6 years ago
Alternatives and similar repositories for Hi-DMM:
Users that are interested in Hi-DMM are comparing it to the libraries listed below
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆60Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- ☆23Updated 4 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- ☆15Updated 2 years ago
- DASS HLS Compiler☆29Updated last year
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆17Updated 7 months ago
- Dataset for ML-guided Accelerator Design☆36Updated 5 months ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- ☆26Updated 5 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆65Updated last year
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆45Updated this week
- A hardware synthesis framework with multi-level paradigm☆38Updated 3 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- ☆15Updated 2 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆33Updated 2 months ago
- Domain-Specific Architecture Generator 2☆20Updated 2 years ago
- ☆26Updated 7 years ago
- A list of our chiplet simulaters☆32Updated 3 weeks ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆28Updated 4 years ago
- Heterogeneous simulator for DECADES Project☆32Updated 11 months ago