Alternatives and similar repositories for bitfiltrator:

Users that are interested in bitfiltrator are comparing it to the libraries listed below

• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆44Updated 2 years ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆31Updated 9 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated last month
• b224hisl / rioschip
  ☆33Updated 2 years ago
• mattvenn / gtkwave-python-filter-process
  ☆33Updated 4 years ago
• AngeloJacobo / DDR3-Notes
  My notes for DDR3 SDRAM controller
  ☆32Updated 2 years ago
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• craigjb / fuse-zynq
  Generate Zynq configurations without using the vendor GUI
  ☆30Updated last year
• antmicro / rowhammer-tester
  ☆60Updated 2 months ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 9 months ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 4 months ago
• mortbopet / NetCracker
  NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between…
  ☆16Updated 4 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆80Updated 6 months ago
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆16Updated 2 weeks ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆75Updated 4 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆68Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 7 months ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆36Updated last year
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆25Updated 2 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• merlinepedra25 / Xilinx-Unprotect
  ☆50Updated 2 years ago
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆41Updated 3 months ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆76Updated 3 years ago
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆18Updated 4 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆40Updated 4 years ago