Alternatives and similar repositories for bitfiltrator

Users that are interested in bitfiltrator are comparing it to the libraries listed below

• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆46Updated 2 years ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆32Updated 9 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 10 months ago
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆38Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• AngeloJacobo / DDR3-Notes
  My notes for DDR3 SDRAM controller
  ☆35Updated 2 years ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆38Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆67Updated 8 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆83Updated this week
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆78Updated 4 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆67Updated last week
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆20Updated 4 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆45Updated last year
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆27Updated 2 years ago
• antmicro / rowhammer-tester
  ☆62Updated 3 weeks ago
• craigjb / fuse-zynq
  Generate Zynq configurations without using the vendor GUI
  ☆30Updated last year
• mortbopet / NetCracker
  NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between…
  ☆17Updated 4 years ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆34Updated 2 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆55Updated 2 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆17Updated 2 months ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆69Updated 3 years ago
• plex1 / SpinalDev
  Docker Development Environment for SpinalHDL
  ☆20Updated 9 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆71Updated 2 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆43Updated 4 months ago