kiabuzz / CompressedLUTLinks
A tool to generate optimized hardware files for univariate functions.
☆29Updated last year
Alternatives and similar repositories for CompressedLUT
Users that are interested in CompressedLUT are comparing it to the libraries listed below
Sorting:
- ☆16Updated 2 years ago
- DASS HLS Compiler☆29Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆63Updated 4 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆124Updated 2 years ago
- ☆87Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆58Updated 11 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆50Updated 2 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- A DSL for Systolic Arrays☆81Updated 6 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 3 months ago
- ☆60Updated this week
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 2 months ago
- Next generation CGRA generator☆114Updated this week
- NeuraLUT-Assemble☆41Updated 3 weeks ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 3 weeks ago
- CGRA framework with vectorization support.☆35Updated last week
- Project repo for the POSH on-chip network generator☆50Updated 5 months ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆47Updated 6 months ago
- ☆27Updated 5 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆36Updated last month
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆44Updated last year
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated last month
- An Open-Hardware CGRA for accelerated computation on the edge.☆33Updated last year
- ☆29Updated 7 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆61Updated 3 years ago