kiabuzz / CompressedLUTLinks
A tool to generate optimized hardware files for univariate functions.
☆29Updated last year
Alternatives and similar repositories for CompressedLUT
Users that are interested in CompressedLUT are comparing it to the libraries listed below
Sorting:
- NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions☆32Updated 2 months ago
- ☆15Updated 2 years ago
- ☆59Updated last month
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- DASS HLS Compiler☆29Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆49Updated last year
- An Open-Hardware CGRA for accelerated computation on the edge.☆28Updated 8 months ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆36Updated 2 weeks ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆44Updated 8 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆46Updated 2 months ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆34Updated 4 months ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- ☆86Updated last year
- ☆27Updated 5 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- ☆35Updated 2 months ago
- ☆71Updated 2 years ago
- ☆58Updated 5 years ago
- A hardware synthesis framework with multi-level paradigm☆39Updated 4 months ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- CGRA framework with vectorization support.☆30Updated 3 weeks ago
- ☆59Updated last week
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆57Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 3 months ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆27Updated 2 years ago