A flexible framework for analyzing and transforming FPGA netlists. Official repository.
☆106Feb 12, 2025Updated last year
Alternatives and similar repositories for spydrnet
Users that are interested in spydrnet are comparing it to the libraries listed below
Sorting:
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- A c project for EDIF format parse.☆14May 10, 2016Updated 9 years ago
- Tools for working with circuits as graphs in python☆126Nov 17, 2023Updated 2 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Mar 17, 2021Updated 4 years ago
- ☆16Jan 25, 2026Updated last month
- Loam system models☆16Dec 30, 2019Updated 6 years ago
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 6 years ago
- EDIF netlist checker tool☆27Oct 24, 2022Updated 3 years ago
- Cross EDA Abstraction and Automation☆41Nov 17, 2025Updated 3 months ago
- D3.js and ELK based schematic visualizer☆115Feb 27, 2024Updated 2 years ago
- A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite☆44Oct 21, 2019Updated 6 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆233Updated this week
- OpenDesign Flow Database☆17Oct 31, 2018Updated 7 years ago
- This is a SpyDrNet Plugin for a physical design related transformations☆16Jun 13, 2025Updated 8 months ago
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago
- A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COrouti…☆21Dec 24, 2023Updated 2 years ago
- A fork of Yosys that integrates the CellIFT pass☆13Jul 23, 2025Updated 7 months ago
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated 11 months ago
- magma circuits☆265Oct 19, 2024Updated last year
- A framework for FPGA emulation of mixed-signal systems☆39Jul 28, 2021Updated 4 years ago
- GNN-RE datasets for circuit recognition☆56May 16, 2023Updated 2 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆450Updated this week
- A standalone structural (gate-level) verilog parser☆40Feb 2, 2026Updated last month
- Code repository for Coppelia tool☆23Nov 12, 2020Updated 5 years ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆446Aug 24, 2025Updated 6 months ago
- mantle library☆44Dec 20, 2022Updated 3 years ago
- ☆46Sep 13, 2024Updated last year
- A Java framework focused on rapid prototyping of new CAD algorithms for FPGA compilation.☆25Dec 17, 2019Updated 6 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆47Feb 12, 2026Updated 3 weeks ago
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- Example of Test Driven Design with VUnit☆16Nov 22, 2021Updated 4 years ago
- An abstraction library for interfacing EDA tools☆756Feb 18, 2026Updated 2 weeks ago
- LogicCircuit is a program that helps build/simulate simple circuits using logic gates. It is meant to teach people the basics of how logi…☆10Feb 16, 2026Updated 3 weeks ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- Open-source FPGA research and prototyping framework.☆210Aug 8, 2024Updated last year
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 7 years ago
- A hardware model checker for hyperproperties☆18Jun 14, 2024Updated last year
- Photonic Integrated ELectronics. Microservices to codesign photonics, electronics, quantum, and more.☆59Jul 1, 2025Updated 8 months ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆119May 14, 2025Updated 9 months ago