Alternatives and similar repositories for spydrnet

Users that are interested in spydrnet are comparing it to the libraries listed below

• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆118Updated last week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆114Updated last year
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆36Updated 2 weeks ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆147Updated 11 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆60Updated 3 years ago
• efabless / mpw_precheck
  ☆40Updated 3 months ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆49Updated 6 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆48Updated last month
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆40Updated last year
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆58Updated 4 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 7 months ago
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆63Updated 3 weeks ago
• pieter3d / simview
  ☆79Updated last year
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆92Updated 3 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 11 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆69Updated this week
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆44Updated 4 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated last week
• pulp-platform / svase
  ☆32Updated 5 months ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 10 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆68Updated 9 months ago
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆101Updated 4 months ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated 10 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆66Updated this week
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆116Updated 2 weeks ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆67Updated 2 weeks ago