byuccl / spydrnetLinks
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
☆104Updated 10 months ago
Alternatives and similar repositories for spydrnet
Users that are interested in spydrnet are comparing it to the libraries listed below
Sorting:
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- Determines the modules declared and instantiated in a SystemVerilog file☆49Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 5 months ago
- A SystemVerilog source file pickler.☆60Updated last year
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Running Python code in SystemVerilog☆71Updated 7 months ago
- An automatic clock gating utility☆51Updated 8 months ago
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Updated 11 months ago
- Framework Open EDA Gui☆74Updated last year
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆79Updated last year
- ☆44Updated 5 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆69Updated 3 months ago
- SystemVerilog frontend for Yosys☆186Updated this week
- Python script to transform a VCD file to wavedrom format☆82Updated 3 years ago
- Tools for working with circuits as graphs in python☆127Updated 2 years ago
- SpinalHDL Hardware Math Library☆94Updated last year
- A Standalone Structural Verilog Parser☆99Updated 3 years ago
- Automatic generation of real number models from analog circuits☆47Updated last year
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated last month
- ideas and eda software for vlsi design☆51Updated this week
- Making cocotb testbenches that bit easier☆36Updated 2 months ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- ☆137Updated last year
- Sphinx Extension which generates various types of diagrams from Verilog code.☆64Updated 2 years ago
- Python library for operations with VCD and other digital wave files☆53Updated last month
- Builds, flow and designs for the alpha release☆54Updated 6 years ago
- Simple parser for extracting VHDL documentation☆73Updated last year
- ☆88Updated 2 months ago