utisam / blifLinks
A library to parse BLIF (Berkeley Logic Interchange Format) files.
☆10Updated 10 years ago
Alternatives and similar repositories for blif
Users that are interested in blif are comparing it to the libraries listed below
Sorting:
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated last year
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- ☆68Updated 3 years ago
- pulp_soc is the core building component of PULP based SoCs☆82Updated 11 months ago
- FPGA tool performance profiling☆105Updated last year
- An automatic clock gating utility☆52Updated 9 months ago
- Builds, flow and designs for the alpha release☆54Updated 6 years ago
- ☆58Updated 10 months ago
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆91Updated 5 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆122Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- ideas and eda software for vlsi design☆51Updated last week
- YosysHQ SVA AXI Properties☆43Updated 3 years ago
- ☆114Updated 5 years ago
- Equivalence checking with Yosys☆57Updated this week
- Determines the modules declared and instantiated in a SystemVerilog file☆51Updated last year
- An implementation of RISC-V☆47Updated last month
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- Automatic SystemVerilog linting in github actions with the help of Verible☆36Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆68Updated 3 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated 2 months ago
- An open source PDK using TIGFET 10nm devices.☆56Updated 3 years ago
- Python interface to FPGA interchange format☆41Updated 3 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆184Updated 9 months ago