ztgao / ConvNN_FPGA_Accelerator
☆13Updated 8 years ago
Related projects: ⓘ
- verilog CNN generator for FPGA☆32Updated 3 years ago
- CNN accelerator☆26Updated 7 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆19Updated 6 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- ☆23Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆26Updated last year
- The Verilog source code for DRUM approximate multiplier.☆26Updated last year
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆20Updated 6 years ago
- Generic FIFO implementation with optional FWFT☆53Updated 4 years ago
- Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs☆47Updated 7 years ago
- ☆31Updated 2 years ago
- ☆12Updated this week
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆41Updated 3 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆16Updated 11 years ago
- SoC Based on ARM Cortex-M3☆24Updated 4 months ago
- DMA controller for CNN accelerator☆12Updated 7 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆40Updated 4 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆103Updated 7 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆15Updated 7 years ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆12Updated 6 months ago
- ☆63Updated 2 years ago
- General Purpose AXI Direct Memory Access☆44Updated 4 months ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆39Updated 3 years ago
- ☆63Updated 9 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 3 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆15Updated 6 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆15Updated 6 years ago