ztgao / ConvNN_FPGA_AcceleratorLinks
☆14Updated 9 years ago
Alternatives and similar repositories for ConvNN_FPGA_Accelerator
Users that are interested in ConvNN_FPGA_Accelerator are comparing it to the libraries listed below
Sorting:
- verilog CNN generator for FPGA☆34Updated 4 years ago
- CNN accelerator☆27Updated 8 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs☆48Updated 7 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆20Updated 7 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 5 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- EE 260 Winter 2017: Advanced VLSI Design☆64Updated 8 years ago
- Convolution Neural Network of vgg19 model in verilog☆47Updated 7 years ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- Project where we conceptualized and designed a simple neural network accelerator, loosely based on the Eyeriss architecture, to accelerat…☆11Updated 5 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆18Updated 7 years ago
- ☆29Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago
- ☆65Updated 6 years ago
- SoC Based on ARM Cortex-M3☆32Updated last month
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆19Updated 11 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆15Updated 8 years ago
- ☆66Updated 3 years ago
- Updated version of the XUP Workshops☆18Updated 6 years ago
- 使用Verilog设计的带四舍五入功能的浮点加法器☆20Updated 13 years ago
- ☆75Updated 10 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12Updated 4 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Updated 7 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago