ztgao / ConvNN_FPGA_Accelerator
☆13Updated 8 years ago
Related projects ⓘ
Alternatives and complementary repositories for ConvNN_FPGA_Accelerator
- verilog CNN generator for FPGA☆32Updated 3 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆19Updated 6 years ago
- ☆82Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆26Updated last year
- round robin arbiter☆68Updated 10 years ago
- Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs☆47Updated 7 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆106Updated 7 years ago
- Updated version of the XUP Workshops☆17Updated 6 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆40Updated 4 years ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆12Updated 8 months ago
- ☆25Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆28Updated last year
- CNN accelerator☆26Updated 7 years ago
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆23Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆17Updated 11 years ago
- Convolution Neural Network of vgg19 model in verilog☆43Updated 6 years ago
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆48Updated 7 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- ☆64Updated 2 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆19Updated 5 years ago
- Verilog Code for a JPEG Decoder☆31Updated 6 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆41Updated 3 years ago
- OpenCL Labs for PAPAA Summer School 2016 Edition☆46Updated 7 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆20Updated 6 years ago
- This is an open CNN accelerator for everyone to use☆14Updated 5 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆19Updated 5 years ago