twomonkeyclub / UARTLinks
ARM中通过APB总线连接的UART模块
☆68Updated 5 years ago
Alternatives and similar repositories for UART
Users that are interested in UART are comparing it to the libraries listed below
Sorting:
- ☆69Updated 9 years ago
- ☆38Updated 10 years ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- AXI总线连接器☆105Updated 5 years ago
- AXI DMA 32 / 64 bits☆121Updated 11 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago
- Cortex M0 based SoC☆75Updated 4 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆22Updated 3 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆132Updated 4 years ago
- 视频旋转(2019FPGA大赛)☆37Updated 5 years ago
- AXI Interconnect☆53Updated 4 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆25Updated 5 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆49Updated 5 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆109Updated 7 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆34Updated 3 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- PCIE 5.0 Graduation project (Verification Team)☆80Updated last year
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆55Updated 5 years ago
- An uvm verification env for ahb2apb bridge☆56Updated 4 years ago
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆224Updated 2 years ago
- IC Verification & SV Demo☆54Updated 4 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆149Updated 7 years ago
- APB to I2C☆43Updated 11 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago