ultraembedded / core_jpeg_decoderLinks
HW JPEG decoder wrapper with AXI-4 DMA
☆36Updated 5 years ago
Alternatives and similar repositories for core_jpeg_decoder
Users that are interested in core_jpeg_decoder are comparing it to the libraries listed below
Sorting:
- UART -> AXI Bridge☆69Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- SPI-Flash XIP Interface (Verilog)☆48Updated 4 years ago
- A 32 point radix-2 FFT module written in Verilog☆25Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Updated 7 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆79Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- Implementation of the PCIe physical layer☆60Updated 6 months ago
- USB -> AXI Debug Bridge☆42Updated 4 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆34Updated 5 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆82Updated 3 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆91Updated last year
- Engineering Program on RTL Design for FPGA Accelerator☆33Updated 5 years ago
- AXI Interconnect☆56Updated 4 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- High-performance FPGA-based JPEG codec accelerator☆13Updated 7 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- DDR3 SDRAM controller☆18Updated 11 years ago
- use Verilog HDL implemente bicubic interpolation in FPGA☆29Updated 6 years ago
- ☆20Updated 3 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆24Updated 7 years ago
- ☆23Updated 6 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- A Verilog implementation of a processor cache.☆34Updated 8 years ago
- APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS☆28Updated 2 years ago