arpitp / ssd-controllerLinks
Open Source SSD Controller. NVMe and Lightstor variants
☆16Updated 11 years ago
Alternatives and similar repositories for ssd-controller
Users that are interested in ssd-controller are comparing it to the libraries listed below
Sorting:
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago
- Computational Storage Device based on the open source project OpenSSD.☆29Updated 5 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated 3 weeks ago
- corundum work on vu13p☆23Updated 2 years ago
- Open-Channel Open-Way Flash Controller☆19Updated 4 years ago
- ☆35Updated last year
- ☆34Updated 3 years ago
- ☆36Updated 5 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Updated 6 years ago
- Simple demo showing how to use the ping pong FIFO☆15Updated 9 years ago
- The official NaplesPU hardware code repository☆19Updated 6 years ago
- An open-source RTL NVMe controller IP for Xilinx FPGA.☆56Updated 4 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆12Updated last year
- ☆32Updated this week
- ☆27Updated 3 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆31Updated last week
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆19Updated 4 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆39Updated last year
- ☆12Updated 3 years ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆26Updated 2 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆18Updated last year
- RISC-V soft-core PEs for TaPaSCo☆23Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated this week
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- PCI Express controller model☆69Updated 3 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆20Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago