Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.
☆17Aug 31, 2020Updated 5 years ago
Alternatives and similar repositories for Image-Compression
Users that are interested in Image-Compression are comparing it to the libraries listed below
Sorting:
- Image processing on FPGA using verilog☆26Dec 5, 2022Updated 3 years ago
- Microshift Compression: An Efficient Image Compression Algorithm for Hardware☆34Apr 21, 2021Updated 4 years ago
- High-performance FPGA-based JPEG codec accelerator☆13Dec 1, 2018Updated 7 years ago
- JPEG2000 compression coder on Xilinx Virtex 5 FPGA☆16Jul 17, 2013Updated 12 years ago
- ☆17Jul 23, 2018Updated 7 years ago
- An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码…☆308Sep 18, 2024Updated last year
- ☆12Aug 25, 2022Updated 3 years ago
- visualization program for vlp-16 based on a viz class☆10Feb 8, 2017Updated 9 years ago
- The CNN based on the Xilinx Vivado HLS☆37Oct 27, 2021Updated 4 years ago
- This repository contains some introductory level review about learning about FPGA Design including some tutorials, links to websites and …☆40Apr 5, 2025Updated 10 months ago
- JPEG Encoder Verilog☆80Oct 31, 2022Updated 3 years ago
- MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/☆10Feb 4, 2022Updated 4 years ago
- "PLI-TDC: Super Fine Delay-Time Based Physical-Layer Identification with Time-to-Digital Converter for In-Vehicle Networks" ACM ASIACCS 2…☆13Feb 11, 2026Updated 2 weeks ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆17Feb 20, 2019Updated 7 years ago
- FPGA图像处理-- 车牌定位,包括二值化,腐蚀,膨胀,sobel边缘检测,水平投影和垂直投影等☆51Mar 17, 2023Updated 2 years ago
- This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.☆13Aug 12, 2020Updated 5 years ago
- SOC system using verilog on FPGA devices.☆10Jan 11, 2016Updated 10 years ago
- 在FPGA端实现JPEG编码(开发中……☆13Oct 17, 2024Updated last year
- ☆10Jul 6, 2015Updated 10 years ago
- An FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器,用来进行无损图像压缩。☆104Sep 18, 2024Updated last year
- Multi Layer Perceptron by Vivado HLS for Xilinx FPGA implementation☆12Dec 26, 2016Updated 9 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- ☆15Jun 7, 2022Updated 3 years ago
- Unit testing for cocotb☆11Aug 6, 2023Updated 2 years ago
- Methods of Mathematical Physics☆12Feb 10, 2021Updated 5 years ago
- This repository contains source code for CNN layers of ALexNet using Xilinx HLS Vivado.☆10Jun 25, 2022Updated 3 years ago
- ☆14Jan 17, 2019Updated 7 years ago
- A library that offers functionality to use Decawave's DW1000 chips/modules with Arduino.☆13Jan 18, 2022Updated 4 years ago
- ZCU102 two IMX274 camera design.☆12Feb 3, 2023Updated 3 years ago
- Verilog Model for W25Q128JVxIM Serial Flash Memory☆17Jun 7, 2020Updated 5 years ago
- Implementation of tappped delay line TDC on FPGA☆13Dec 28, 2022Updated 3 years ago
- Toy OFDM Communication System with FPGA☆12Dec 13, 2021Updated 4 years ago
- ☆14Dec 15, 2017Updated 8 years ago
- Learn UVM by small projects☆18Aug 31, 2021Updated 4 years ago
- Huffman encoding core (Vivado HLS Project)☆12Oct 15, 2019Updated 6 years ago
- ☆13Sep 28, 2021Updated 4 years ago
- LDF、QDF、RDA、MQDF☆16Nov 25, 2017Updated 8 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Aug 25, 2021Updated 4 years ago