MaharshSuryawala / Image-Compression
Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.
☆16Updated 4 years ago
Alternatives and similar repositories for Image-Compression:
Users that are interested in Image-Compression are comparing it to the libraries listed below
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆63Updated 8 months ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- This is a demo for still image compression application☆13Updated 7 years ago
- ☆19Updated 2 years ago
- AXI Interconnect☆47Updated 3 years ago
- ☆25Updated 3 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆21Updated 6 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 3 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆48Updated 5 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆30Updated 3 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 4 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- AXI4 BFM in Verilog☆32Updated 8 years ago
- FFT implement by verilog_测试验证已通过☆55Updated 8 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- ☆36Updated 9 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆21Updated 3 years ago
- SPI interface connect to APB BUS with Verilog HDL☆31Updated 3 years ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆25Updated 8 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆54Updated last year