MaharshSuryawala / Image-CompressionLinks
Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.
☆16Updated 4 years ago
Alternatives and similar repositories for Image-Compression
Users that are interested in Image-Compression are comparing it to the libraries listed below
Sorting:
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆64Updated 9 months ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆42Updated last year
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 3 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆32Updated 3 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- AHB DMA 32 / 64 bits☆55Updated 10 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆32Updated 6 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 4 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆54Updated last year
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆48Updated 5 years ago
- SPI interface connect to APB BUS with Verilog HDL☆32Updated 3 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆54Updated 3 years ago
- AXI Interconnect☆49Updated 3 years ago
- FFT implement by verilog_测试验证已通过☆57Updated 8 years ago
- ☆25Updated 4 years ago
- This is a demo for still image compression application☆13Updated 7 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆15Updated 2 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆48Updated 5 years ago
- ☆31Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago