MaharshSuryawala / Image-Compression
Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.
☆16Updated 4 years ago
Alternatives and similar repositories for Image-Compression:
Users that are interested in Image-Compression are comparing it to the libraries listed below
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆32Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆45Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆60Updated 7 months ago
- Image processing on FPGA using verilog☆21Updated 2 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆36Updated 8 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- 基于FPGA的三速以太网UDP协议栈设计☆22Updated last year
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆17Updated 6 years ago
- ☆28Updated 5 years ago
- fpga跑sobel识别算法☆29Updated 4 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆14Updated 2 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆30Updated 6 years ago
- RTL Verilog library for various DSP modules☆85Updated 3 years ago
- A 32 point radix-2 FFT module written in Verilog☆22Updated 4 years ago
- ☆25Updated 3 years ago
- FFT implement by verilog_测试验证已通过☆54Updated 8 years ago
- Step by step tutorial for building CortexM0 SoC☆36Updated 2 years ago
- Bilinear interpolation realizes image scaling based on FPGA☆24Updated 4 years ago
- SPI interface connect to APB BUS with Verilog HDL☆28Updated 3 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆21Updated 3 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆30Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆50Updated last year
- This is a demo for still image compression application☆13Updated 6 years ago
- APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS☆22Updated 2 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆48Updated 3 years ago