TheMozg / spi-amba-simulationLinks
ITMO SystemC & Verilog assignments - AMBA AHB and SPI
☆21Updated 7 years ago
Alternatives and similar repositories for spi-amba-simulation
Users that are interested in spi-amba-simulation are comparing it to the libraries listed below
Sorting:
- ☆20Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆21Updated 5 years ago
- ☆25Updated 4 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- ☆16Updated 6 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- Generate UVM testbench framework template files with Python 3☆26Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆20Updated 5 years ago
- Generic AXI to AHB bridge☆17Updated 10 years ago
- Verification IP for UART protocol☆17Updated 4 years ago
- Design and UVM-TB of RISC -V Microprocessor☆20Updated 11 months ago
- Implementation of the PCIe physical layer☆40Updated 3 weeks ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆11Updated 4 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆43Updated last year
- Various low power labs using sky130☆12Updated 3 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- UVM resource from github, run simulation use YASAsim flow☆27Updated 5 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- General Purpose AXI Direct Memory Access☆50Updated last year
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 6 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆14Updated 10 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 3 years ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago