Lianghao-Yuan / AHB_Bus_Matrix
☆35Updated 9 years ago
Alternatives and similar repositories for AHB_Bus_Matrix:
Users that are interested in AHB_Bus_Matrix are comparing it to the libraries listed below
- AHB DMA 32 / 64 bits☆52Updated 10 years ago
- AXI Interconnect☆47Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- Generic AXI to AHB bridge☆16Updated 10 years ago
- APB to I2C☆39Updated 10 years ago
- ahb scram controller, design and verification☆27Updated 6 years ago
- AXI总线连接器☆93Updated 4 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- ☆65Updated 3 years ago
- ☆16Updated 2 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆66Updated 5 years ago
- Verification IP for APB protocol☆56Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆57Updated 11 months ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆28Updated 2 years ago
- Step by step tutorial for building CortexM0 SoC☆37Updated 2 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆22Updated 2 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆41Updated 8 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆30Updated 2 years ago
- UART design in SV and verification using UVM and SV☆39Updated 5 years ago
- SPI interface connect to APB BUS with Verilog HDL☆25Updated 3 years ago
- ARM中通过APB总线连接的UART模块☆60Updated 4 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- FFT implement by verilog_测试验证已通过☆52Updated 8 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- AXI DMA 32 / 64 bits☆103Updated 10 years ago
- AXI4 BFM in Verilog☆31Updated 8 years ago
- ☆23Updated 3 years ago
- ☆57Updated 8 years ago
- an open source uvm verification platform for e200 (riscv)☆26Updated 6 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆20Updated 5 years ago