Alternatives and similar repositories for simple_SoC

Users that are interested in simple_SoC are comparing it to the libraries listed below

• jm2000 / RISCV-FPU
  Basic floating-point components for RISC-V processors
  ☆10Updated 7 years ago
• PacoReinaCampo / MPSoC-NoC
  Network on Chip for MPSoC
  ☆26Updated last week
• shalan / MS_DMAC_AHBL
  A Direct Memory Access Controller (DMAC) with AHB-lite bus interface
  ☆13Updated 8 months ago
• PacoReinaCampo / vhdl2verilog
  Hardware Description Language Translator
  ☆16Updated last week
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆24Updated 5 years ago
• pulp-platform / axi_node
  AXI X-Bar
  ☆19Updated 5 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆22Updated last week
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• freecores / double_fpu
  double_fpu_verilog
  ☆15Updated 10 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆20Updated 5 years ago
• zhouzaixin / arm_soc
  ☆14Updated 5 years ago
• pulp-platform / hier-icache
  ☆12Updated 3 months ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• apriya-ram / AXI_FIFO_BFM
  AXI4 with a FIFO integrated with VIP
  ☆19Updated last year
• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆15Updated 4 months ago
• zhouqinghua / zqh_riscv
  zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…
  ☆37Updated 3 years ago
• enjoy-digital / litex_verilog_axi_test
  Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.
  ☆16Updated 2 years ago
• armleo / ArmleoCPU
  ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set
  ☆6Updated 2 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆39Updated 4 years ago
• freecores / theia_gpu
  Theia: ray graphic processing unit
  ☆20Updated 10 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆32Updated 3 weeks ago
• fengyulin1996 / Verilog-DSP
  FIR，FFT based on Verilog
  ☆13Updated 7 years ago
• muneebullashariff / pulpino_soc_uvm_testbench
  UVM testbench for verifying the Pulpino SoC
  ☆13Updated 5 years ago
• kaitoukito / YSYX-NJU-Group
  YSYX RISC-V Project NJU Study Group
  ☆16Updated 5 months ago
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆13Updated 8 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆30Updated last week
• PacoReinaCampo / SoC-DV
  System on Chip verified with UVM/OSVVM/FV
  ☆27Updated last week
• AmrElsersy / DMA
  DMA Hardware Description with Verilog
  ☆14Updated 5 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 10 years ago
• jchengX / MAC_BFM
  wifi
  ☆11Updated 7 years ago