Corey-Maler / simple_SoCLinks
Small and simple, primitive SoC with GPU, CPU, RAM, GPIO
☆13Updated 8 years ago
Alternatives and similar repositories for simple_SoC
Users that are interested in simple_SoC are comparing it to the libraries listed below
Sorting:
- ☆16Updated 6 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆10Updated 7 years ago
- ☆12Updated 9 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆12Updated 5 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 9 years ago
- Direct Access Memory for MPSoC☆13Updated 3 months ago
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆14Updated 6 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Updated 6 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 7 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Updated 5 years ago
- Simple demo showing how to use the ping pong FIFO☆15Updated 9 years ago
- SoC Based on ARM Cortex-M3☆33Updated 3 months ago
- 位宽和深度可定制的异步FIFO☆13Updated last year
- Generic AXI master stub☆19Updated 11 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- ☆13Updated 8 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- AXI4 with a FIFO integrated with VIP☆21Updated last year
- ☆20Updated 3 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- AXI X-Bar☆19Updated 5 years ago
- Verification IP for UART protocol☆20Updated 5 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 4 years ago
- UVM testbench for verifying the Pulpino SoC☆14Updated 5 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 8 months ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago