Corey-Maler / simple_SoC
Small and simple, primitive SoC with GPU, CPU, RAM, GPIO
☆13Updated 8 years ago
Alternatives and similar repositories for simple_SoC
Users that are interested in simple_SoC are comparing it to the libraries listed below
Sorting:
- ☆14Updated 5 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆13Updated 7 months ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- Hardware Formal Verification☆15Updated 4 years ago
- Basic floating-point components for RISC-V processors☆10Updated 7 years ago
- ☆16Updated 4 years ago
- AXI4 with a FIFO integrated with VIP☆18Updated last year
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- SoC Based on ARM Cortex-M3☆30Updated last week
- Network on Chip for MPSoC☆26Updated this week
- wifi☆11Updated 7 years ago
- ☆16Updated 6 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated last week
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆18Updated 3 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 3 months ago
- System on Chip verified with UVM/OSVVM/FV☆26Updated last week
- A risc v based architecture to develop a core/ processor which is capable of Matrix MAC Operations☆9Updated last year
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated 2 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 4 months ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆11Updated 4 years ago
- AXI X-Bar☆19Updated 5 years ago
- Hardware Description Language Translator☆16Updated last week
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆30Updated last week
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆19Updated 5 years ago
- Quad cluster of RISC-V cores with peripherals and local memory☆24Updated 3 years ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…☆16Updated 8 years ago