RoaLogic / apb4_gpio
General Purpose IO with APB4 interface
☆12Updated 11 months ago
Alternatives and similar repositories for apb4_gpio:
Users that are interested in apb4_gpio are comparing it to the libraries listed below
- Platform Level Interrupt Controller☆40Updated 11 months ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 2 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- ☆26Updated 2 weeks ago
- Universal Advanced JTAG Debug Interface☆17Updated 11 months ago
- RISC-V compliant Timer IP☆12Updated 11 months ago
- ☆10Updated last year
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year
- Multi-Technology RAM with AHB3Lite interface☆23Updated 11 months ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆26Updated 3 years ago
- JTAG Test Access Port (TAP)☆33Updated 10 years ago
- USB -> AXI Debug Bridge☆36Updated 3 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 4 months ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated this week
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. Work in Progress.☆11Updated 6 months ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 3 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆54Updated 3 months ago
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆20Updated 4 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆19Updated 5 years ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- AXI X-Bar☆19Updated 5 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- ☆23Updated 7 years ago
- ☆13Updated last month
- LIS Network-on-Chip Implementation☆29Updated 8 years ago