SPI通信实现FLASH读写
☆17Mar 18, 2020Updated 6 years ago
Alternatives and similar repositories for Verilog_spi_flash
Users that are interested in Verilog_spi_flash are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- OpenMIPS——《自己动手写CPU》处理器部分☆22Mar 4, 2017Updated 9 years ago
- 使用国产FPGA厂商安路公司的开发板做的一款基于FPGA的智能导盲杖系统。利用百度LBS开放平台做到自主导航，与Arduino互联实现PID算法，摄像头识别红绿灯，超声波自主避障，语音识别，一键拨打紧急联系人等等☆33Nov 28, 2019Updated 6 years ago
- 软件无线电，使用FPGA进行正交解调。☆23Feb 18, 2019Updated 7 years ago
- Small (Q)SPI flash memory programmer in Verilog☆69Nov 5, 2022Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆49Oct 24, 2021Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Mirror of NeTV FPGA Verilog Code☆15Jan 21, 2012Updated 14 years ago
- ☆14Aug 23, 2023Updated 2 years ago
- ARM中通过APB总线连接的UART模块☆71Feb 21, 2020Updated 6 years ago
- FPGA implementation of the hector_slam algorithm using only lidar data☆10Jul 3, 2022Updated 3 years ago
- 学习AXI接口，以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 9 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- 用Altera FPGA芯片自制CPU☆42Aug 10, 2014Updated 11 years ago
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆27Mar 9, 2016Updated 10 years ago
- spi memory controller☆24Jan 5, 2017Updated 9 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 400 nm SiO2 capacitor simulation of interface trap formation with state transitions in Sentaurus TCAD☆16May 26, 2017Updated 8 years ago
- ☆20Nov 18, 2022Updated 3 years ago
- 本项目设计一个可以产生21种音阶的电子琴，由PS2键盘完成输入，在Basys2板识别处理后，产生特定频率声音，最后通过Pmod_AMP模块发出。☆10Jul 21, 2019Updated 6 years ago
- PYNQ-T9 repo. Use antminer t9 (with 1GbE) as PYNQ devboard.☆14Nov 7, 2024Updated last year
- FPGA简单入门☆12Nov 17, 2020Updated 5 years ago
- ☆24Mar 27, 2022Updated 4 years ago
- Histogram Equalization Implementation by MATLAB☆12Nov 15, 2016Updated 9 years ago
- 新一代北斗卫星导航监测接收机的FPGA实现☆31May 17, 2016Updated 9 years ago
- Computing calibrated prediction intervals for neural network regressors☆10May 28, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- HDMI + GPU-pipeline + FFT☆14Mar 4, 2016Updated 10 years ago
- Mirror of the OpenFabrics NVMe Windows driver repository☆18Jul 11, 2017Updated 8 years ago
- Cortex_m0软核源码，可以在FPGA上直接跑，包含UART、定时器这些外设，可以用keil写用户代码。可以看看《Cortex-M0 全可编程SoC原理及实现》这本书☆26Mar 15, 2021Updated 5 years ago
- 这是我所开发的两个项目，包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆100Sep 25, 2017Updated 8 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago
- Implemented The UART with FIFO☆15Jul 4, 2019Updated 6 years ago
- Implementation of the CMAC keyed hash function using AES as block cipher.☆16Apr 2, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- Prediction Intervals: Split Normal Mixture from Quality-Driven Deep Ensembles. Published at Uncertainty in AI (UAI) 2020.☆11Aug 31, 2020Updated 5 years ago
- 本应用可以帮助你将国网的电费、用电量数据接入homeassistant，并且储存到数据库。☆19Sep 15, 2023Updated 2 years ago
- verilog modules☆15May 4, 2020Updated 6 years ago
- Verification IP for APB protocol☆34Sep 9, 2020Updated 5 years ago
- 这是使用FPGA开发CMOS的两个真实项目，之前的fpga_design仅是一个未完善的版本，同时也删除了一些与项目无关的东西☆36Nov 11, 2017Updated 8 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago