Yongxiang-Guo / Verilog_spi_flashLinks
SPI通信实现FLASH读写
☆14Updated 5 years ago
Alternatives and similar repositories for Verilog_spi_flash
Users that are interested in Verilog_spi_flash are comparing it to the libraries listed below
Sorting:
- FPGA 同步FIFO与异步FIFO☆31Updated 6 years ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 10 years ago
- 异步FIFO的内部实现☆24Updated 6 years ago
- ☆25Updated 4 years ago
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆22Updated 2 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 10 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- ☆16Updated 6 years ago
- ☆14Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Updated 7 years ago
- ☆18Updated 3 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆66Updated 3 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆48Updated 5 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- spi memory controller☆22Updated 8 years ago
- 基于FPGA的FFT☆18Updated 6 years ago
- Project in Course named DESIGN AND IMPLEMENTATION OF COMMUNICATION PROTOCOLS in FCU☆14Updated 10 years ago
- ☆20Updated 2 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆18Updated 10 months ago
- digital recognition base on FPGA☆14Updated 5 years ago
- 软件无线电,使用FPGA进行正交解调。☆22Updated 6 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago