Alternatives and similar repositories for apb_timer

Users that are interested in apb_timer are comparing it to the libraries listed below

• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆43Updated last year
• verilator / example-systemverilog
  ☆40Updated last year
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆35Updated 4 months ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆47Updated 3 years ago
• RClabiisc / I2SRV64-SS-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆26Updated last year
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆28Updated 7 years ago
• rajshadow / 4-way-set-associative-cache-verilog
  Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
  ☆41Updated 8 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 8 months ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆18Updated 4 years ago
• pulp-platform / axi2apb
  ☆21Updated 5 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆24Updated last year
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆45Updated last year
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆30Updated 4 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆64Updated 4 years ago
• AmrElsersy / DMA
  DMA Hardware Description with Verilog
  ☆17Updated 5 years ago
• Ashwin-Rajesh / Verilog_projects
  Some beginner projects using verilog HDL, along with some documentation on basic syntax
  ☆12Updated 4 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆30Updated 4 months ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆60Updated 5 years ago
• odedyo / Median-filter-verilog-
  Design a median filter for a Generic RGB image.
  ☆14Updated 6 years ago
• chipsalliance / uvm-verilator
  ☆99Updated 2 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated last week
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆60Updated 2 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆22Updated 7 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆60Updated last year
• Noman-10xe / AXI-DMA-Verification
  Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM
  ☆37Updated 3 months ago
• asveske / apb_vip
  APB VIP (UVM)
  ☆15Updated 7 years ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆15Updated last year
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago