Alternatives and similar repositories for apb_timer

Users that are interested in apb_timer are comparing it to the libraries listed below

• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• pulp-platform / axi2apb
  ☆20Updated 5 years ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆21Updated 10 months ago
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• AmrElsersy / DMA
  DMA Hardware Description with Verilog
  ☆14Updated 5 years ago
• rajshadow / 4-way-set-associative-cache-verilog
  Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
  ☆41Updated 8 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆35Updated 9 years ago
• pulp-platform / axi_llc
  ☆29Updated last month
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆17Updated last year
• bvnirliptha / AMBA-3-AHB--LITE-Protocol-Design-and-Verification
  -Designed and Verified a Bus Functional Model of AHB-LITE Protocol from scratch. -Developed Assertion based verification IP to verify the…
  ☆21Updated 9 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆26Updated 5 years ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆17Updated 4 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆50Updated last year
• ljgibbslf / basic_cache_core
  ☆28Updated 4 years ago
• ehao222 / ASIC-design-example-RISC-CPU
  Base on Synopsys platform using VCS,DC,ICC,PT.
  ☆11Updated 4 years ago
• yadav-sachin / Multilevel-Cache-Controller
  Cache Controller for a multi-level Cache memory using four-way set-associative mapping with write-back, no-write allocate and LRU policy.…
  ☆9Updated 4 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆43Updated last year
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated this week
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆30Updated last week
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• prasadp4009 / 2-way-Set-Associative-Cache-Controller
  Synthesizable and Parameterized Cache Controller in Verilog
  ☆44Updated last year
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago
• ShonTaware / LowPower
  Various low power labs using sky130
  ☆12Updated 3 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆22Updated 6 years ago
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆14Updated last year
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆33Updated 4 months ago