Very simple Cortex-M1 SoC design based on ARM DesignStart
☆19Jan 25, 2022Updated 4 years ago
Alternatives and similar repositories for SimpleSoC
Users that are interested in SimpleSoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆28Oct 8, 2018Updated 8 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆20Jan 28, 2022Updated 4 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock m…☆16Nov 4, 2020Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆72May 8, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆13Jul 14, 2024Updated 2 years ago
- AES☆16Oct 4, 2022Updated 4 years ago
- A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board☆13Sep 7, 2018Updated 8 years ago
- DMA core compatible with AHB3-Lite☆13Mar 30, 2019Updated 7 years ago
- AXI-Stream USB 2.0 HS Device Bridge (Verilog)☆16Apr 17, 2025Updated last year
- Animals classification using CNN☆10Aug 29, 2019Updated 7 years ago
- AHB Bus lite v3.0☆17Aug 7, 2019Updated 7 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 12 years ago
- ☆10Apr 2, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The open-source release of "SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip"☆11Oct 7, 2023Updated 3 years ago
- ☆28Oct 23, 2026Updated last week
- Education kit for teaching introductory Arm-based system-on-chip design on FPGA with lectures and practical labs (educational)☆175Oct 7, 2025Updated last year
- BaseJump Open-Source Hardware Accelerator Packages and Sockets☆12Jul 7, 2025Updated last year
- This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efables…☆12Dec 6, 2023Updated 2 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- Convert Xilinx FPGA bitstream from the .bit format (as generated by Vivado) into the .bin format (as expected by Linux fpga_manager)☆18Sep 5, 2023Updated 3 years ago
- A simple UVM project. The DUT(RTL) is a simple amplifier.☆10Sep 28, 2022Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆50May 10, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Senior Design☆13Jan 26, 2025Updated last year
- Verilog CAN controller that is compatible to the SJA 1000.☆20Apr 17, 2021Updated 5 years ago
- Spiking Neural Network Accelerator☆15May 18, 2022Updated 4 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- ☆11Oct 13, 2022Updated 4 years ago
- My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA☆13Jun 26, 2018Updated 8 years ago
- ☆14Jun 16, 2025Updated last year
- ☆11Oct 9, 2023Updated 3 years ago
- Cortex_m0软核源码,可以在FPGA上直接跑,包含UART、定时器这些外设,可以用keil写用户代码。可以看看《Cortex-M0 全可编程SoC原理及实现》这本书☆27Mar 15, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP☆19Nov 9, 2023Updated 2 years ago
- Cortex-M0 DesignStart Wrapper☆24Aug 11, 2019Updated 7 years ago
- ☆11Dec 1, 2025Updated 11 months ago
- Tiva C: UART, I2C, SPI, SSI☆14Oct 13, 2019Updated 7 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆86Oct 7, 2022Updated 4 years ago
- This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI S…☆14Mar 7, 2021Updated 5 years ago
- ☆39Aug 12, 2015Updated 11 years ago