Very simple Cortex-M1 SoC design based on ARM DesignStart
☆17Jan 25, 2022Updated 4 years ago
Alternatives and similar repositories for SimpleSoC
Users that are interested in SimpleSoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆17Jan 28, 2022Updated 4 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- Step by step tutorial for building CortexM0 SoC☆39Mar 29, 2022Updated 3 years ago
- SoC Based on ARM Cortex-M3☆37May 16, 2025Updated 10 months ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 11 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68May 8, 2020Updated 5 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆17Feb 9, 2026Updated last month
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆48May 10, 2024Updated last year
- Verilog CAN controller that is compatible to the SJA 1000.☆16Apr 17, 2021Updated 4 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- Cortex_m0软核源码，可以在FPGA上直接跑，包含UART、定时器这些外设，可以用keil写用户代码。可以看看《Cortex-M0 全可编程SoC原理及实现》这本书☆26Mar 15, 2021Updated 5 years ago
- This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock m…☆14Nov 4, 2020Updated 5 years ago
- KiCad symbols and footprints created by myself or modified from KiCad library for my projects.☆15Nov 16, 2025Updated 4 months ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Examples for Gowin Tang Nano 4k FPGA-board.☆13Aug 13, 2022Updated 3 years ago
- Senior Design☆12Jan 26, 2025Updated last year
- An FPGA design for simulating biological neurons☆17Jul 5, 2024Updated last year
- ☆38Aug 12, 2015Updated 10 years ago
- Commonly used code for projects using ARM Cortex-M with ChibiOS☆16Jun 22, 2016Updated 9 years ago
- ☆11Oct 9, 2023Updated 2 years ago
- RISC-V-5 stage pipelined in verilog☆10Jul 24, 2020Updated 5 years ago
- ☆30Jul 9, 2025Updated 8 months ago
- minimal code to access ps DDR from PL☆22Oct 18, 2019Updated 6 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆76Oct 7, 2022Updated 3 years ago
- zynqmp_cam_isp_demo linux软件项目☆22Dec 18, 2022Updated 3 years ago
- Education kit for teaching introductory Arm-based system-on-chip design on FPGA with lectures and practical labs (educational)☆156Oct 7, 2025Updated 5 months ago
- Spiking Neural Network Accelerator☆15May 18, 2022Updated 3 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 6 years ago
- Brilliantly Radical Artificially Intelligent Neural Machine☆18Dec 28, 2017Updated 8 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆213Aug 23, 2023Updated 2 years ago
- A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated …☆66Feb 18, 2024Updated 2 years ago
- ⚙️ 基于 Zynq-7 全可编程 SoC 的设计☆39Dec 31, 2021Updated 4 years ago
- ☆20Jun 18, 2022Updated 3 years ago
- Update STM32L4 firmware via I2C/UART using default STM32 bootloader☆15Jan 20, 2023Updated 3 years ago
- A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration☆46Nov 24, 2025Updated 3 months ago
- Research enablement kit for designing and prototyping a Cortex-M0–based SoC with custom IP integration (education, research)☆16Jun 13, 2025Updated 9 months ago
- 一个基于ModBus RTU协议的PLC继电器从站☆11Dec 2, 2015Updated 10 years ago
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆30Dec 1, 2016Updated 9 years ago