Alternatives and similar repositories for SimpleSoC

Users that are interested in SimpleSoC are comparing it to the libraries listed below

• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆43Updated 3 years ago
• ultraembedded / fpga_test_soc
  A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
  ☆33Updated 5 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆65Updated 5 years ago
• FDU-ME-ARC / NVMeCHA
  ☆19Updated 4 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆39Updated 4 years ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆41Updated 11 years ago
• dpiegdon / verilog-can
  Verilog CAN controller that is compatible to the SJA 1000.
  ☆13Updated 4 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆76Updated 2 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 6 months ago
• giuseppedongiovanni / nvme_comp_storage
  Computational Storage Device based on the open source project OpenSSD.
  ☆27Updated 4 years ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆34Updated 4 years ago
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆20Updated this week
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• aignacio / mpsoc_example
  ☆60Updated 3 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆45Updated 5 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed3
  DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8
  ☆15Updated 3 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆60Updated 4 years ago
• yigitbektasgursoy / SDRAM_Verilog
  Verilog HDL implementation of SDRAM controller and SDRAM model
  ☆29Updated last year
• iammituraj / FIFOs
  Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
  ☆18Updated last year
• subutai-attic / pars
  ☆30Updated 8 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• DUNE / pl-nvme
  ☆36Updated 5 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆58Updated 5 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆85Updated 5 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆63Updated 4 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆68Updated 7 years ago
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆22Updated 7 years ago
• 0xArt / RGMII_Ethernet_Transceiver_Verilog
  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
  ☆30Updated 2 years ago