siorpaes / SimpleSoC
Very simple Cortex-M1 SoC design based on ARM DesignStart
☆17Updated 3 years ago
Alternatives and similar repositories for SimpleSoC:
Users that are interested in SimpleSoC are comparing it to the libraries listed below
- DDR4 Simulation Project in System Verilog☆35Updated 10 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆12Updated 3 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- ☆36Updated last year
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆31Updated 5 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆14Updated 2 years ago
- ☆24Updated last month
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆13Updated last year
- SPI-Flash XIP Interface (Verilog)☆36Updated 3 years ago
- ☆16Updated 5 years ago
- ☆25Updated 3 years ago
- Platform Level Interrupt Controller☆37Updated 10 months ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆36Updated 3 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 3 years ago
- ☆14Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- Design and UVM-TB of RISC -V Microprocessor☆15Updated 9 months ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆18Updated 6 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- Extensible FPGA control platform☆59Updated last year
- ☆59Updated 3 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- ☆19Updated 5 years ago
- Implementation of the PCIe physical layer☆35Updated 2 months ago