AHB Bus lite v3.0
☆17Aug 7, 2019Updated 6 years ago
Alternatives and similar repositories for ahb_lite_bus
Users that are interested in ahb_lite_bus are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47May 10, 2024Updated last year
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆18Sep 2, 2023Updated 2 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- Multi-Technology RAM with AHB3Lite interface☆24May 10, 2024Updated last year
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆28Oct 8, 2018Updated 7 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- AHB3-Lite Interconnect☆109May 10, 2024Updated last year
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆18Jan 25, 2022Updated 4 years ago
- Test Realtime FIR/IIR Filter using FMAC (Filter Math ACCcelerator). The FMAC unit is built around a fixed point multiplier and accumulato…☆13Nov 10, 2021Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68May 8, 2020Updated 5 years ago
- ☆24Oct 8, 2019Updated 6 years ago
- A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games☆24Nov 15, 2018Updated 7 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 11 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆29May 11, 2021Updated 4 years ago
- AMBA bus generator including AXI, AHB, and APB☆122Jul 29, 2021Updated 4 years ago
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated last year
- Repository for keeping code from YouTube Tutorials☆11Sep 27, 2022Updated 3 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Mar 17, 2022Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆36Mar 9, 2017Updated 9 years ago
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 14 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆26Mar 8, 2026Updated last month
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- UART 16550 core☆39Jul 17, 2014Updated 11 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆78Oct 7, 2022Updated 3 years ago
- ⚙️ 基于 Zynq-7 全可编程 SoC 的设计☆41Dec 31, 2021Updated 4 years ago
- General Purpose IO with APB4 interface☆16May 10, 2024Updated last year
- Testbenches for HDL projects☆23Apr 8, 2026Updated last week
- SystemVerilog Logger☆19Apr 6, 2026Updated last week
- CAN-bus Controller with AXI4-lite Interface☆17Mar 4, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- power spectrum using fft, waveforms and amplitude spectrums for delta, alpha, gamma, beta and theta bands☆12Sep 28, 2016Updated 9 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆15Dec 1, 2023Updated 2 years ago
- ☆38Aug 12, 2015Updated 10 years ago
- The memory model was leveraged from micron.☆30Mar 24, 2018Updated 8 years ago
- Bluespec H.264 Decoder☆12Jul 17, 2014Updated 11 years ago
- MMC (and derivative standards) host controller☆25Sep 14, 2020Updated 5 years ago