aignacio / ahb_lite_busView external linksLinks
AHB Bus lite v3.0
☆17Aug 7, 2019Updated 6 years ago
Alternatives and similar repositories for ahb_lite_bus
Users that are interested in ahb_lite_bus are comparing it to the libraries listed below
Sorting:
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Sep 2, 2023Updated 2 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47May 10, 2024Updated last year
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- AHB3-Lite Interconnect☆109May 10, 2024Updated last year
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68May 8, 2020Updated 5 years ago
- SystemVerilog Logger☆19Sep 30, 2025Updated 4 months ago
- Testbenches for HDL projects☆22Updated this week
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Jan 25, 2022Updated 4 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆20Jul 29, 2014Updated 11 years ago
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated last year
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- MMC (and derivative standards) host controller☆25Sep 14, 2020Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- Generic AXI master stub☆19Jul 17, 2014Updated 11 years ago
- Open FPGA Modules☆24Oct 8, 2024Updated last year
- ☆23Oct 8, 2019Updated 6 years ago
- CAN-bus Controller with AXI4-lite Interface☆15Mar 4, 2025Updated 11 months ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆24Nov 7, 2018Updated 7 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆25Nov 24, 2019Updated 6 years ago
- A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games☆23Nov 15, 2018Updated 7 years ago
- AXI support for Migen/MiSoC☆28Jun 5, 2025Updated 8 months ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆28Oct 8, 2018Updated 7 years ago
- Build an open source, extremely simple DMA.☆23Feb 17, 2019Updated 6 years ago
- Multi-Technology RAM with AHB3Lite interface☆25May 10, 2024Updated last year
- General Purpose AXI Direct Memory Access☆62May 12, 2024Updated last year
- The memory model was leveraged from micron.☆28Mar 24, 2018Updated 7 years ago
- An FPGA-based NetTLP adapter☆27Mar 10, 2020Updated 5 years ago
- ☆11May 31, 2016Updated 9 years ago
- ☆27May 11, 2021Updated 4 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆75Oct 7, 2022Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆119Jul 29, 2021Updated 4 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- AHB to APB Bridge VIP☆31Mar 4, 2019Updated 6 years ago
- Baseband Receiver IP for GPS like DSSS signals☆40May 19, 2020Updated 5 years ago
- USB -> AXI Debug Bridge☆42Jun 5, 2021Updated 4 years ago