A simple Verilog SPI master / slave implementation featuring all 4 modes.
☆87Dec 7, 2020Updated 5 years ago
Alternatives and similar repositories for verilog_spi
Users that are interested in verilog_spi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An open-source Verilog implementation of Serial Peripheral Interface protocol with simulation support for efficient data exchange.☆16Dec 26, 2023Updated 2 years ago
- A collection of SPI related cores☆22Nov 12, 2024Updated last year
- SPI interface connect to APB BUS with Verilog HDL☆43Jun 27, 2021Updated 5 years ago
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆21Dec 15, 2019Updated 6 years ago
- Interface Protocol in Verilog☆52Aug 2, 2019Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆71May 8, 2020Updated 6 years ago
- SPI Slave for FPGA in Verilog and VHDL☆233May 11, 2024Updated 2 years ago
- This is a SPI Master Module Written in Verilog☆14Aug 9, 2018Updated 8 years ago
- Connecting FPGA and Arduino using SPI.☆25Apr 30, 2022Updated 4 years ago
- Verilog SPI master and slave☆63Jan 4, 2016Updated 10 years ago
- SPI Master for FPGA - VHDL and Verilog☆348Aug 22, 2023Updated 3 years ago
- Simple SPI-based communication between FPGA and MCU, using EP4CE15 and STM32F407 as an example☆14Feb 16, 2024Updated 2 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆11Aug 15, 2020Updated 6 years ago
- DC-SCM LTPI Reference Implementation☆25Jan 13, 2026Updated 7 months ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆23Jul 7, 2024Updated 2 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆20Jan 5, 2023Updated 3 years ago
- A Verilog RTL model of a simple 8-bit RISC processor☆21Jan 15, 2019Updated 7 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆28Sep 8, 2024Updated last year
- QEMU port for ARCv2 Processors☆16Apr 9, 2026Updated 4 months ago
- A simple implementation of a UART modem in Verilog.☆193Nov 10, 2021Updated 4 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆31Apr 29, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Simple 8-bit UART realization on Verilog HDL.☆120Apr 27, 2024Updated 2 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆36Sep 6, 2018Updated 8 years ago
- Some crazy experiments about using a FPGA to transmit a TV signal old-style☆13Oct 13, 2018Updated 7 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆15Jul 31, 2024Updated 2 years ago
- ☆10Jun 7, 2022Updated 4 years ago
- ☆17Apr 14, 2023Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- Single Port RAM, Dual Port RAM, FIFO☆34May 17, 2022Updated 4 years ago
- Present Crypto Engine in Verilog☆12Feb 27, 2016Updated 10 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆35May 17, 2020Updated 6 years ago
- USB2.0 Verilog☆20Apr 21, 2019Updated 7 years ago
- Verilog I2C interface for FPGA implementation☆725Feb 27, 2025Updated last year
- SPI通信实现FLASH读写☆17Mar 18, 2020Updated 6 years ago
- PID controller on an FPGA with custom RS232 addressing protocol.☆26Sep 7, 2021Updated 5 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆26Mar 8, 2026Updated 6 months ago
- This demo will help you get started with AWS IoT Secure Tunneling, that helps customers establish bidirectional communication to remote d…☆20Updated this week